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%s/Relatvie/Relative'
Signed-off-by: Heinrich Schuchardt <[email protected]>
Acked-by: Peng Fan <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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The default value of 0x800000 (8 MB) is somewhat limiting for us, as our
compressed kernel may grow up to around 4 MB. By choosing the commonly
used value of 0x2000000 (32 MB), we are definitely on the safe side.
This rather large amount should be fine, as we have 128 MB of RAM.
Signed-off-by: Ezra Buehler <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Jiaxun Yang <[email protected]> says:
This is a huge series which promoted MIPS/Boston target into a
usable state, with fixes to drivers and general framework issues
I found in this process.
I also converted the target to OF_UPSTREAM.
This target is covered by QEMU, to test on QEMU:
```
make boston64r6el_defconfig
make
qemu-system-mips64el -M boston -cpu I6500 -bios ./u-boot.bin -nographic
```
Link: https://lore.kernel.org/r/[email protected]
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Paul had left MIPS a couple of years ago, his email address is
no longer valid.
Replace it with his kenrel.org email, which has been used in
kernel and QEMU, in case we still want to reach him.
Signed-off-by: Jiaxun Yang <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
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We can now boot with upstream devicetree.
Reviewed-by: Sumit Garg <[email protected]>
Signed-off-by: Jiaxun Yang <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
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It is required to make OF_UPSTREAM work.
Reviewed-by: Sumit Garg <[email protected]>
Signed-off-by: Jiaxun Yang <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
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In upstream devicetree, clk_boston is a child of syscon node
and there is no "regmap" property for clk_boston node.
Try to check parent device first to look for syscon.
Signed-off-by: Jiaxun Yang <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
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Provide default environment variables on image loading address
to make the board useful.
Signed-off-by: Jiaxun Yang <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
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This is a PC-like platform board.
Enable drivers for most on-board devices to make it useful.
Signed-off-by: Jiaxun Yang <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
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Some drivers need this header.
Provide this dummy header as riscv did.
Signed-off-by: Jiaxun Yang <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
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Remove hard dependencies to arch headers, get clock from clk
subsystem if arch clock function is not available, align
compatible strings with devicetree binding.
No functional change on existing platforms, just get it build
on other platforms.
Signed-off-by: Jiaxun Yang <[email protected]>
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Ensure that we are using correct physical/virtual address for
DMA buffer write and hardware register settings.
The convention is: in ahci_ioports all pointers are virtual,
that will be converted to physical address when writing to
hardware registers or into sg/cmd_tbl.
Also fixed 64bit physical address support for dwc_ahsata, ensure
higher bits are written into registers/sg properly.
Use memalign for allocating aligned buffer in dwc_ahsata so we
don't have to do our own alignment in driver.
Signed-off-by: Jiaxun Yang <[email protected]>
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For MIPS we are always looking gd->dram in virtual address so
PCI_MAP_SYSTEM_MEMORY should always be enabled.
If in future we ever want to make it physical we have to set
ARCH_MAP_SYSMEM.
Signed-off-by: Jiaxun Yang <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
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Boston has a very limited memory range for PCI controllers, where
1MB can't easily fit into it.
Make alignment boundary of PCI memory resource allocation a Kconfig
option and default to 0x10000 for boston.
Signed-off-by: Jiaxun Yang <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
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Probe size of ecam from devicetree properly and cap accessible
bus number accorading to ecam region size to ensure we don't go
beyond hardware address space.
Also disable all interrupts to ensure errors are handled silently.
Signed-off-by: Jiaxun Yang <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
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Heinrich Schuchardt <[email protected]> says:
For QEMU we have developed supporting passsing through ACPI tables.
This functionality has been broken multipled times due to missing CI
builds.
* Two new defconfigs qemu_arm64_acpi and qemu-riscv64_smode_acpi.
* Assign the defconfigs to the respective maintainers.
Link: https://lore.kernel.org/r/[email protected]
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Jerome Forissier <[email protected]> says:
Enable CONFIG_UNIT_TEST in most of the configs/qemu*_defconfig files
to increase test coverage in CI, and fix what needs to be fixed.
Link: https://lore.kernel.org/r/[email protected]
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Jerome Forissier <[email protected]> says:
There is a bug in the print_guid() unit test in test/common/print.c when
PARTITION_TYPE_GUID is not enabled but either CMD_EFIDEBUG or EFI are.
The first patch fixes the issue and the second one enables UNIT_TEST in
the qemu_arm64 defconfig so that the unit tests are run in CI (this
platform has CMD_EFIDEBUG so the bug applies).
Link: https://lore.kernel.org/r/[email protected]
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Enable CONFIG_UNIT_TEST in configs/qemu_arm64_defconfig so that the unit
tests are run in CI.
Signed-off-by: Jerome Forissier <[email protected]>
Reviewed-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
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The name defined for PARTITION_SYSTEM_GUID in list_guid[] depends on
configuration options. It is "system" if CONFIG_PARTITION_TYPE_GUID is
enabled or "System Partition" if CONFIG_CMD_EFIDEBUG or CONFIG_EFI are
enabled. In addition, the unit test in test/common/print.c is incorrect
because it expects only "system" (or a hex GUID).
Make things more consistent by using a clear and unique name: "EFI
System Partition" whatever the configuration, and update the unit test
accordingly.
Signed-off-by: Jerome Forissier <[email protected]>
Suggested-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
Reviewed-by: Heinrich Schuchardt <[email protected]>
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Add the follow board to VIRT which otherwise would be unmaintained:
* qemu-riscv64_smode_acpi_defconfig
Signed-off-by: Heinrich Schuchardt <[email protected]>
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Add a configuration that supports ACPI.
Signed-off-by: Heinrich Schuchardt <[email protected]>
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Add the following boards to VIRT which otherwise would be unmaintained.
* qemu_arm64_acpi_defconfig
* qemu_arm64_lwip_defconfig
Signed-off-by: Heinrich Schuchardt <[email protected]>
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Add a qemu_arm64 variant that supports ACPI.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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The qemu* "generic" targets (i.e. not those emulating a particular
board) are typically used for testing as many features as possible,
especially in CI so it makes sense to have UNIT_TEST enabled for
all of the defconfigs for these targets.
Not enabling UNIT_TEST in qemu-x86_defconfig due to:
LD u-boot
ld.bfd: section .rel.dyn VMA wraps around address space
ld.bfd: section .start16 LMA [fffff800,fffff86f] overlaps section .rel.dyn LMA [ffffb77c,0002ac93]
make: *** [Makefile:1824: u-boot] Error 1
Suggested-by: Tom Rini <[email protected]>
Signed-off-by: Jerome Forissier <[email protected]>
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Some test commands (such as "false", or the empty string) need
CONFIG_HUSH_PARSER=y. Fix test/cmd/command.c.
Signed-off-by: Jerome Forissier <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-i2c
i2c updates for v2025.07-rc1
- omap24xx_i2c: Enable Repeated Start functionality
add Repeated Start functionality for the DM_I2C xfer
API (omap_i2c_xfer()
from Aniket Limaye
- mediatek i2c driver
fixes from Martin
- add end marker for struct udevice_id mtk_i2c_ids
- remove duplicate entry in mt_i2c_regs_v1
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https://source.denx.de/u-boot/custodians/u-boot-socfpga
This pull request contains updates for the SoCFPGA platform, targeting
the 2025.07 release cycle. Highlights include enhancements to Agilex5
support, improvements in DDR error handling, and bridge reset handling
for SoC64 devices.
Key updates:
Agilex5 platform enhancements:
* New MMU region mappings and memory layout updates using
LMB_ARCH_MEM_MAP.
* Fixes for bloblist configuration, kernel FIT image generation, and
VAB flow enablement.
* GPIO pin control added for SDIO selection.
* Marvell PHY driver enabled in defconfig.
Agilex5 / SoC64 DDR subsystem:
* Added ECC debug improvements for IOSSM.
* Introduced LPDDR inline ECC support.
* Resolved size calculation overflow in memory driver.
SoC64 improvements:
* Enhanced mailbox communication with the SDM to reflect various
boot stage transitions.
* Implemented F2S bridge reset support and updated related reset
manager registers.
* Expanded SoC64 CPU info reporting.
General maintenance:
* Additional peripherals released from reset for Arria10.
* Cleanup of legacy or incorrect Kconfig implications.
This patch set has been tested on Agilex 5 devkit.
Passing all pipeline tests at:
https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/25867
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This removes a duplicate entry in mt_i2c_regs_v1[].
Signed-off-by: Martin Schiller <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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This adds the missing empty entry at the end of mtk_i2c_ids[].
Signed-off-by: Martin Schiller <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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Add a Kconfig option to disable sending Stop conditions between multiple
i2c_msgs within a single xfer. Enable this config by default for ARCH_K3
platforms.
Signed-off-by: Aniket Limaye <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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Repeated Start Condition (Sr) can be used to transfer multiple i2c msgs
without sending a Stop condition (P). So far, the driver default was to
always send a Stop condition after every i2c msg.
Add support for a config option (CONFIG_SYS_I2C_OMAP24XX_REPEATED_START)
to disable sending the Stop condition by default. If this config is
enabled, Stop condition will be sent only if explicitly requested in the
msg flags OR if it is the last msg in the transfer.
Consequently, handle the Repeated Start condition (Sr) in the next msg
by not calling the wait_for_bb() check since it will simply timeout in
the absence of a stop condition (BB will be 1 until Stop is programmed)
Signed-off-by: Aniket Limaye <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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Remove __omap24_i2c_read/write() usage from omap_i2c_xfer() in favour of
the more flexible __omap24_i2c_xfer_msg().
Consequently, these are also no longer needed when DM_I2C is enabled.
New function __omap24_i2c_xfer_msg() will take care of individual read
OR write transfers with a target device. It goes through below sequence:
- Program the provided Target Chip address (OMAP_I2C_SA_REG)
- Program the provided Data len (OMAP_I2C_CNT_REG)
- Program the provided Control register flags (OMAP_I2C_CON_REG)
- Read from or Write to the provided Data buffer (OMAP_I2C_DATA_REG)
For a detailed programming guide, refer to the TRM[0] (12.1.3.4 I2C
Programming Guide).
This patch by itself should be a transparent change. However this is
needed for implementing a proper Repeated Start (Sr) functionality for
i2c_msgs.
Previous implementation for omap_i2c_xfer called __omap24_i2c_read/write
functions, with hardcoded addr=0 and alen=0 for each i2c_msg. Each of
these calls would program the registers always with a Stop bit set, not
allowing for a repeated start between i2c_msgs in the same xfer().
[0]: https://www.ti.com/lit/zip/spruj28 (TRM)
Signed-off-by: Aniket Limaye <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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Remove unused piece of code under CONFIG_I2C_REPEATED_START which does
not have any Kconfig entry at all.
Signed-off-by: Aniket Limaye <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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ECC debug information was enhanced to improve the readability of error
messages.
Signed-off-by: Tingting Meng <[email protected]>
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In-line ECC support was added for LPDDR by reserving the last one-eighth
of the memory space for ECC data. Full memory initialization using the
BIST MEM INIT mailbox command, based on address and size, is required to
correctly generate ECC data and enable proper ECC logic verification.
Signed-off-by: Tingting Meng <[email protected]>
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Cache allocation for dirty writes in the CCU system cache was disabled
for performance optimization.
Signed-off-by: Tingting Meng <[email protected]>
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LMB_ARCH_MEM_MAP is enabled, and lmb_arch_add_memory() is introduced to
correctly handle memory reservations for the second and third DDR
memory banks.
Signed-off-by: Tingting Meng <[email protected]>
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MMU mapping regions were added for the second and third DDR memory banks.
Signed-off-by: Tingting Meng <[email protected]>
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As of 2025, Altera is now a standalone company prior to
being a subsidiary of Intel Corporation.
Update CPU info printout naming from Intel to Altera.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
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Use GPIO hogging method in device tree to set SDIO_SEL pin (portb3)
direction as output with value 0 after power-on reset.
This is to ensure stable 0V voltage reading from SDIO_SEL GPIO pin
after board init.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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CONFIG_BLOBLIST_FIXED and CONFIG_BLOBLIST_ADDR options were
unintentionally removed during recent external updates to the defconfig.
This patch restores the missing entries to ensure proper board
functionality. No new features are introduced.
Fixes: d6a53f523afe ("spl: Add an SPL_HAVE_INIT_STACK option")
Signed-off-by: Tingting Meng <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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The use of both "imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION" and
"imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE" here is wrong as
those are both part of the same choice statement. Furthermore you cannot
select/imply something from a choice statement, it must be a "default ...
if ..." construct within the choice statement in question.
Signed-off-by: Tom Rini <[email protected]>
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Vendor Authorized Boot flow configurations are enabled for boards
based on Agilex5 SoCFPGA. Also, required changes are made to the
SoCFPGA make file for building and linking relevant secure source
code files.
Signed-off-by: Naresh Kumar Ravulapalli <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Load and entry addresses are corrected for Agilex5 SoCFPGA board
which would enable to generate the kernel itb file with the right
addresses.
Signed-off-by: Naresh Kumar Ravulapalli <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Enable Marvell Ethernet PHYs support for Agilex5 defconfig
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Send out "HPS_STAGE_NOTIFY" mailbox command to the
Secure Device Manager (SDM) in SPL to inform SDM on
FSBL execution.
This is necessary for the SDM to recognize that the
FSBL stage has begun its execution and should be
made as early as possible in the FSBL process.
Therefore, the mailbox will initialize and send out
the notification right after the completion of timer
initialization.
Signed-off-by: Mahesh Rao <[email protected]>
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Enable reset support for FPGA2SDRAM bridge for Stratix10, as well as
FPGA2SoC and SoC2FPGA bridges for all SoC64 families.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Add reset manager registers in preparation for F2S bridge reset
support as well as the mask support to enable/disable the bridges.
Mask value:
BIT0: soc2fpga
BIT1: lwhps2fpga
BIT2: fpga2soc
These bridges are available only in Stratix10:
BIT3: f2sdram0
BIT4: f2sdram1
BIT5: f2sdram2
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Introducing a new mailbox command "HPS_STAGE_NOTIFY" to notify Secure
Device Manager (SDM) on the stage of HPS code execution.
Generally, there are three main code execution stages: First Stage Boot
Loader (FSBL) which is U-Boot SPL, Second Stage Boot Loader (SSBL) which
is U-Boot, and the Operating System (OS) which is Linux.
This enables the user to query the SDM for HPS error details.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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