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For armv8 we are adding proper page permissions for the relocated U-Boot
binary. Add a weak function that can be used across architectures to change
the page permissions
Tested-by: Neil Armstrong <[email protected]> # on AML-S905X-CC
Signed-off-by: Ilias Apalodimas <[email protected]>
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As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.
Reported-by: Jonas Karlman <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.
This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.
Reported-by: Jonas Karlman <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Remove <common.h> from the remainder of the files under arch/arm and
when needed add missing include files directly.
Signed-off-by: Tom Rini <[email protected]>
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Signed-off-by: Wolfgang Denk <[email protected]>
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Move this header out of the common header. Network support is used in
quite a few places but it still does not warrant blanket inclusion.
Note that this net.h header itself has quite a lot in it. It could be
split into the driver-mode support, functions, structures, checksumming,
etc.
Signed-off-by: Simon Glass <[email protected]>
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These functions belong in cpu_func.h. Another option would be cache.h
but that code uses driver model and we have not moved these cache
functions to use driver model. Since they are CPU-related it seems
reasonable to put them here.
Move them over.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances
where these configuration items are conditional on SPL. This commit adds SPL
variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates
the configurations as required.
Acked-by: Alexey Brodkin <[email protected]>
Signed-off-by: Trevor Woerner <[email protected]>
[trini: Make the default depend on the setting for full U-Boot, update
more zynq hardware]
Signed-off-by: Tom Rini <[email protected]>
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Four different boards had different options for enabling cache
that were virtually all the same. This consolidates these
common functions into arch/arm/cpu/arm926ejs/cache.c
This also has the positive side-effect of enabling cache on
the Davinci (da850) boards.
Signed-off-by: Adam Ford <[email protected]>
[trini: Add mach-at91 to the list of consolidations]
Signed-off-by: Tom Rini <[email protected]>
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When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.
In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.
This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.
Signed-off-by: Tom Rini <[email protected]>
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Today, we have cases where we wish to build all of U-Boot in Thumb2 mode for
various reasons. We also have cases where we only build SPL in Thumb2 mode due
to size constraints and wish to build the rest of the system in ARM mode. So
in this migration we introduce a new symbol as well, SPL_SYS_THUMB_BUILD to
control if we build everything or just SPL (or in theory, just U-Boot) in
Thumb2 mode.
Signed-off-by: Tom Rini <[email protected]>
Acked-by: Siarhei Siamashka <[email protected]>
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This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all
cases we are mirroring the values used by the Linux Kernel here. Also,
so long as (and in this case, it is true) we implement flushes in hunks
that are no larger than the smallest implementation (and given that we
mirror the Linux Kernel, again we are fine) it is OK to align higher.
The biggest changes here are that we always use 64 bytes for CPU_V7 even
if for example the underlying core is only 32 bytes (this mirrors
Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the
Linux Kernel) as we do not need multi-platform support (to this degree)
and only the Cavium ThunderX 88xx series has a use for such large
alignment.
Cc: Albert Aribaud <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Prafulla Wadaskar <[email protected]>
Cc: Luka Perkov <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Nagendra T S <[email protected]>
Cc: Vaibhav Hiremath <[email protected]>
Acked-by: Lokesh Vutla <[email protected]>
Cc: Steve Rae <[email protected]>
Cc: Igor Grinberg <[email protected]>
Cc: Nikita Kiryanov <[email protected]>
Cc: Stefan Agner <[email protected]>
Acked-by: Heiko Schocher <[email protected]>
Cc: Mateusz Kulikowski <[email protected]>
Cc: Peter Griffin <[email protected]>
Acked-by: Paul Kocialkowski <[email protected]>
Cc: Anatolij Gustschin <[email protected]>
Acked-by: "Pali Rohár" <[email protected]>
Cc: Adam Ford <[email protected]>
Cc: Steve Sakoman <[email protected]>
Cc: Grazvydas Ignotas <[email protected]>
Cc: Nishanth Menon <[email protected]>
Cc: Stephen Warren <[email protected]>
Cc: Robert Baldyga <[email protected]>
Cc: Minkyu Kang <[email protected]>
Cc: Thomas Weber <[email protected]>
Cc: Masahiro Yamada <[email protected]>
Cc: David Feng <[email protected]>
Cc: Alison Wang <[email protected]>
Cc: Michal Simek <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: York Sun <[email protected]>
Cc: Shengzhou Liu <[email protected]>
Cc: Mingkai Hu <[email protected]>
Cc: Prabhakar Kushwaha <[email protected]>
Cc: Aneesh Bansal <[email protected]>
Cc: Saksham Jain <[email protected]>
Cc: Qianyu Gong <[email protected]>
Cc: Wang Dongsheng <[email protected]>
Cc: Alex Porosanu <[email protected]>
Cc: Hongbo Zhang <[email protected]>
Cc: tang yuantian <[email protected]>
Cc: Rajesh Bhagat <[email protected]>
Cc: Josh Wu <[email protected]>
Cc: Bo Shen <[email protected]>
Cc: Viresh Kumar <[email protected]>
Cc: Hannes Schmelzer <[email protected]>
Cc: Thomas Chou <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Sam Protsenko <[email protected]>
Cc: Bin Meng <[email protected]>
Cc: Christophe Ricard <[email protected]>
Cc: Anand Moon <[email protected]>
Cc: Beniamino Galvani <[email protected]>
Cc: Carlo Caione <[email protected]>
Cc: huang lin <[email protected]>
Cc: Sjoerd Simons <[email protected]>
Cc: Xu Ziyuan <[email protected]>
Cc: "[email protected]" <[email protected]>
Cc: "Ariel D'Alessandro" <[email protected]>
Cc: Kever Yang <[email protected]>
Cc: Samuel Egli <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Hans de Goede <[email protected]>
Cc: Ian Campbell <[email protected]>
Cc: Siarhei Siamashka <[email protected]>
Cc: Boris Brezillon <[email protected]>
Cc: Andre Przywara <[email protected]>
Cc: Bernhard Nortmann <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Ben Whitten <[email protected]>
Cc: Tom Warren <[email protected]>
Cc: Alexander Graf <[email protected]>
Cc: Sekhar Nori <[email protected]>
Cc: Vitaly Andrianov <[email protected]>
Cc: "Andrew F. Davis" <[email protected]>
Cc: Murali Karicheri <[email protected]>
Cc: Carlos Hernandez <[email protected]>
Cc: Ladislav Michl <[email protected]>
Cc: Ash Charles <[email protected]>
Cc: Mugunthan V N <[email protected]>
Cc: Daniel Allred <[email protected]>
Cc: Gong Qianyu <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
Acked-by: Masahiro Yamada <[email protected]>
Acked-by: Chin Liang See <[email protected]>
Tested-by: Stephen Warren <[email protected]>
Acked-by: Paul Kocialkowski <[email protected]>
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This code is common, so move it into a common file.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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When building a Thumb-1-only target with CONFIG_SYS_THUMB_BUILD,
some files fail to build, most of the time because they include
mcr instructions, which only exist for Thumb-2.
This patch introduces a Kconfig option CONFIG_THUMB2 and uses
it to select between Thumb-2 and ARM mode for the aforementioned
files.
Signed-off-by: Albert ARIBAUD <[email protected]>
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Current many cpu use the same flush_cache() function, which just call
the flush_dcache_range().
So implement a weak flush_cache() for all the cpus to use.
In original weak flush_cache() in arch/arm/lib/cache.c, there has some
code for ARM1136 & ARM926ejs. But in the arch/arm/cpu/arm1136/cpu.c and
arch/arm/cpu/arm926ejs/cache.c, there implements a real flush_cache()
function as well. That means the original code for ARM1136 & ARM926ejs
in weak flush_cache() of arch/arm/lib/cache.c is totally useless.
So in this patch remove such code in flush_cache() and only call
flush_dcache_range().
Signed-off-by: Josh Wu <[email protected]>
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Since some driver like ohci, lcd used dcache functions. But some ARM
cpu don't implement the invalidate_dcache_range()/flush_dcache_range()
functions.
To avoid compiling errors this patch adds an weak empty stub function
for all ARM cpu in arch/arm/lib/cache.c.
And ARM cpu still can implemnt its own cache functions on the cpu folder.
Signed-off-by: Josh Wu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Cc: Albert Aribaud <[email protected]>
Signed-off-by: Jeroen Hofstee <[email protected]>
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Signed-off-by: Wolfgang Denk <[email protected]>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <[email protected]>
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Signed-off-by: Marek Vasut <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Albert ARIBAUD <[email protected]>
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We certainly don't want the compiler to reorganise the code for dcache flushing.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Albert ARIBAUD <[email protected]>
Acked-by: Mike Frysinger <[email protected]>
Acked-by: Stefano Babic <[email protected]>
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Misaligned warnings are useful to debug faulty drivers.
A misaligned warning is printed also when the driver
is correct - use debug() instead of printf().
Signed-off-by: Stefano Babic <[email protected]>
CC: Albert Aribaud <[email protected]>
CC: Mike Frysinger <[email protected]>
CC: Marek Vasut <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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Signed-off-by: Marek Vasut <[email protected]>
Cc: Stefano Babic <[email protected]>
Acked-by: Stefano Babic <[email protected]>
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The decompressor expects the L2 cache to be disabled. This fixes booting
some kernels, which have CONFIG_ARM_PATCH_PHYS_VIRT enabled.
Signed-off-by: Michael Walle <[email protected]>
Acked-by: Prafulla Wadaskar <[email protected]>
Cc: Albert ARIBAUD <[email protected]>
Cc: Prafulla Wadaskar <[email protected]>
Cc: Wolfgang Denk <[email protected]>
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Commit 2f3427c added noop cache functions implementation for arm926ejs
to fix compilation of drivers depending on these functions (DaVinci
EMAC in particular).
Unfortunately, the bug was introduced: noop implementation calls
dcache_disable which calls flush_dcache_all which in turn calls
dcache_disable thus creating an infinite loop.
This patch removes noop implementation for flush_dcache_all, we already
have default one in arch/arm/lib/cache.c and it should be used instead.
Signed-off-by: Ilya Yanok <[email protected]>
Tested-by: Matthias Weisser <[email protected]>
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Added noop implementation for dcache operations that will buzz
about missing real implementation and disable the dcache.
This fixes compilation of DaVinci EMAC driver on arm926ejs.
Signed-off-by: Ilya Yanok <[email protected]>
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