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Change is consistent with other SOCs and it is in preparation
for adding SOMs. SOC's related files are moved from cpu/ to
mach-imx/<SOC>.
This change is also coherent with the structure in kernel.
Signed-off-by: Stefano Babic <[email protected]>
CC: Fabio Estevam <[email protected]>
CC: Akshay Bhat <[email protected]>
CC: Ken Lin <[email protected]>
CC: Marek Vasut <[email protected]>
CC: Heiko Schocher <[email protected]>
CC: "Sébastien Szymanski" <[email protected]>
CC: Christian Gmeiner <[email protected]>
CC: Stefan Roese <[email protected]>
CC: Patrick Bruenn <[email protected]>
CC: Troy Kisky <[email protected]>
CC: Nikita Kiryanov <[email protected]>
CC: Otavio Salvador <[email protected]>
CC: "Eric Bénard" <[email protected]>
CC: Jagan Teki <[email protected]>
CC: Ye Li <[email protected]>
CC: Peng Fan <[email protected]>
CC: Adrian Alonso <[email protected]>
CC: Alison Wang <[email protected]>
CC: Tim Harvey <[email protected]>
CC: Martin Donnelly <[email protected]>
CC: Marcin Niestroj <[email protected]>
CC: Lukasz Majewski <[email protected]>
CC: Adam Ford <[email protected]>
CC: "Albert ARIBAUD (3ADEV)" <[email protected]>
CC: Boris Brezillon <[email protected]>
CC: Soeren Moch <[email protected]>
CC: Richard Hu <[email protected]>
CC: Wig Cheng <[email protected]>
CC: Vanessa Maegima <[email protected]>
CC: Max Krummenacher <[email protected]>
CC: Stefan Agner <[email protected]>
CC: Markus Niebel <[email protected]>
CC: Breno Lima <[email protected]>
CC: Francesco Montefoschi <[email protected]>
CC: Jaehoon Chung <[email protected]>
CC: Scott Wood <[email protected]>
CC: Joe Hershberger <[email protected]>
CC: Anatolij Gustschin <[email protected]>
CC: Simon Glass <[email protected]>
CC: "Andrew F. Davis" <[email protected]>
CC: "Łukasz Majewski" <[email protected]>
CC: Patrice Chotard <[email protected]>
CC: Nobuhiro Iwamatsu <[email protected]>
CC: Hans de Goede <[email protected]>
CC: Masahiro Yamada <[email protected]>
CC: Stephen Warren <[email protected]>
CC: Andre Przywara <[email protected]>
CC: "Álvaro Fernández Rojas" <[email protected]>
CC: York Sun <[email protected]>
CC: Xiaoliang Yang <[email protected]>
CC: Chen-Yu Tsai <[email protected]>
CC: George McCollister <[email protected]>
CC: Sven Ebenfeld <[email protected]>
CC: Filip Brozovic <[email protected]>
CC: Petr Kulhavy <[email protected]>
CC: Eric Nelson <[email protected]>
CC: Bai Ping <[email protected]>
CC: Anson Huang <[email protected]>
CC: Sanchayan Maity <[email protected]>
CC: Lokesh Vutla <[email protected]>
CC: Patrick Delaunay <[email protected]>
CC: Gary Bisson <[email protected]>
CC: Alexander Graf <[email protected]>
CC: [email protected]
Reviewed-by: Fabio Estevam <[email protected]>
Reviewed-by: Christian Gmeiner <[email protected]>
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At present CONFIG_CMD_SATA enables the 'sata' command which also brings
in SATA support. Some boards may wish to enable SATA without the command.
Add a separate CONFIG to permit this.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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We repeated partial moves for CONFIG_SYS_NO_FLASH, but this is
not completed. Finish this work by the tool.
During this move, let's rename it to CONFIG_MTD_NOR_FLASH.
Actually, we have more instances of "#ifndef CONFIG_SYS_NO_FLASH"
than those of "#ifdef CONFIG_SYS_NO_FLASH". Flipping the logic will
make the code more readable. Besides, negative meaning symbols do
not fit in obj-$(CONFIG_...) style Makefiles.
This commit was created as follows:
[1] Edit "default n" to "default y" in the config entry in
common/Kconfig.
[2] Run "tools/moveconfig.py -y -r HEAD SYS_NO_FLASH"
[3] Rename the instances in defconfigs by the following:
find . -path './configs/*_defconfig' | xargs sed -i \
-e '/CONFIG_SYS_NO_FLASH=y/d' \
-e 's/# CONFIG_SYS_NO_FLASH is not set/CONFIG_MTD_NOR_FLASH=y/'
[4] Change the conditionals by the following:
find . -name '*.[ch]' | xargs sed -i \
-e 's/ifndef CONFIG_SYS_NO_FLASH/ifdef CONFIG_MTD_NOR_FLASH/' \
-e 's/ifdef CONFIG_SYS_NO_FLASH/ifndef CONFIG_MTD_NOR_FLASH/' \
-e 's/!defined(CONFIG_SYS_NO_FLASH)/defined(CONFIG_MTD_NOR_FLASH)/' \
-e 's/defined(CONFIG_SYS_NO_FLASH)/!defined(CONFIG_MTD_NOR_FLASH)/'
[5] Modify the following manually
- Rename the rest of instances
- Remove the description from README
- Create the new Kconfig entry in drivers/mtd/Kconfig
- Remove the old Kconfig entry from common/Kconfig
- Remove the garbage comments from include/configs/*.h
Signed-off-by: Masahiro Yamada <[email protected]>
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Add clock support for i.MX6SLL.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
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The LCDIF Pixel clock mux is not glitchless, so need
to gate before changing mux.
Also change enable_lcdif_clock prototype with a new input
parameter to indicate disable or enable.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
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Add lcdif clock support for i.MX6SL.
Signed-off-by: Peng Fan <[email protected]>
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The mux for the lcd clock is not glitchless,
so need to first gate the clock before changing the mux.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
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>From RM, per_periph2_clk_sel option3 is:
"derive clock from 198MHz clock (divided 392MHz PLL2 PFD)."
So fix it.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
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This patch extends the imx6 clock code to enable or disable the EIM
slow clock, which in necessary when one wants to use EIM interface t
o read/write from external memory (e.g. NOR).
Signed-off-by: Lukasz Majewski <[email protected]>
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Need to gate ENET clock when switching to a new clock parent, because
the mux is not glitchless.
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Ye.Li <[email protected]>
Cc: Stefano Babic <[email protected]>
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Update Clock settings and CCM register map for i.MX6ULL.
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Cc: Stefano Babic <[email protected]>
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Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content. (both just wrap <asm-generic/errno.h>)
Replace all include directives for <asm/errno.h> with <linux/errno.h>.
Signed-off-by: Masahiro Yamada <[email protected]>
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini <[email protected]>
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According to the IMX6DQRM Reference Manual, the description
of bit 7 (axi_alt_sel) of the CCM_CBCDR register is:
"AXI alternative clock select
0 pll2 396MHz PFD will be selected as alternative clock for AXI root clock
1 pll3 540MHz PFD will be selected as alternative clock for AXI root clock "
The current logic is inverted, so fix it to match the reference manual.
Signed-off-by: Fabio Estevam <[email protected]>
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Typo fix, "PPL2 -> PLL2"
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
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Use simpler runtime cpu dection macros.
i.MX6DL and i.MX6SOLO work the same, so use is_mx6sdl.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
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i.MX6DL and i.MX6SOLO work the same, add i.MX6SOLO support
when enable/disable_ldb_di_clock_sources.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
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Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk tree,
the glitchy parent mux of ldb_di[x]_clk can cause a glitch to enter the
ldb_di_ipu_div divider. If the divider gets locked up, no ldb_di[x]_clk is
generated, and the LVDS display will hang when the ipu_di_clk is sourced from
ldb_di_clk.
To fix the problem, both the new and current parent of the ldb_di_clk should
be disabled before the switch. This patch ensures that correct steps are
followed when ldb_di_clk parent is switched in the beginning of boot.
This patch was ported from the 3.10.17 NXP kernel
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_3.10.17_1.0.1_ga&id=eecbe9a52587cf9eec30132fb9b8a6761f3a1e6d
NXP errata number: ERR009219, EB821
Signed-off-by: Akshay Bhat <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Fabio Estevam <[email protected]>
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Default print ARM clock for clocks command.
Test on i.MX6UL 14x14 evk board:
"
=> clocks
PLL_SYS 792 MHz
PLL_BUS 528 MHz
PLL_OTG 480 MHz
PLL_NET 50 MHz
ARM 396000 kHz
"
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
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The checking with max frequency supported is not correct, because the temp
is calculated by max pre and post dividers. We can decrease any divider to
meet the max frequency limitation. Actually, the calculation below the codes
is doing this way to find best pre and post dividers.
Signed-off-by: Ye Li <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
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Wrong checking for the base_addr paramter with LCDIF1 and LCDIF2. Always
enter the -EINVAL return.
Signed-off-by: Ye Li <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
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Check "Figure 19-5. BUS clock generation" of i.MX 6SoloX Applications
Processor Reference Manual and "Figure 18-5. BUS clock generation" of
i.MX 6UltraLite Applications Processor Reference Manual. If mmdc clk
sources from pll4_main_clk(pll_audio), the calculation is wrong.
Fix mmdc_ch0 clk calculation. Also add PLL_AUDIO/VIDEO support
for decode_pll.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
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cc: Peng Fan <[email protected]>
Signed-off-by: Jeroen Hofstee <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
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On mx6sx, the CCM register bits for GPMI are different as other
mx6 platforms. Modify the GPMI clock function to support mx6sx.
Signed-off-by: Ye.Li <[email protected]>
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Implement mxs_set_lcdclk, enable_lcdif_clock and enable_pll_video.
The three API can be used to configure lcdif related clock when
CONFIG_VIDEO_MXS enabled.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
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We should follow 'read->set/clr bit->write' flow for enable_fec_anatop_clock,
otherwise we may overridden configuration before enable_fec_anatop_clock.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Cc: Fabio Estevam <[email protected]>
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To i.MX6SX/UL, two ethernet interfaces are supported.
Add ENET2 clock support:
1. Introduce a new input parameter "fec_id", only 0 and 1 are allowed.
To value 1, only i.MX6SX/UL can pass the check.
2. Modify board code who use this api to follow new api prototype.
Signed-off-by: Peng Fan <[email protected]>
Cc: Heiko Schocher <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Nikolaos Pasaloukos <[email protected]>
Cc: Stefano Babic <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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1. Add enet, uart, i2c, ipg clock support for i.MX6UL.
2. Correct get_periph_clk, it should account for
MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK.
3. Refactor get_mmdc_ch0_clk to make all i.MX6 share one function,
but not use 'ifdef'.
4. Use CONFIG_FSL_QSPI for enable_qspi_clk, but not #ifdef CONFIG_MX6SX.
5. Use CONFIG_PCIE_IMX for pcie clock settings, use CONFIG_CMD_SATA for
sata clock settings. In this way, we not need "#if defined(CONFIG_MX6Q)
|| defined....", only need one CONFIG_PCIE_IMX in header file.
Signed-off-by: Ye.Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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The i.MX6DQP has a PRG module, need to enable its clock for using IPU.
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Brown Oliver <[email protected]>
Signed-off-by: Ye.Li <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Acked-by: Stefano Babic <[email protected]>
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Since i.MX6QP changes some CCM registers, so modify the clocks settings to
follow the hardware changes.
In c files, use runtime check and discard #ifdef.
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Ye.Li <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Acked-by: Stefano Babic <[email protected]>
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Add I2C4 clock support for i.MX6SX. Since we use runtime check,
but not macro, we need to remove `#ifdef ..` in crm_regs.h, or
gcc will fail to compile the code succesfully.
Making the macros only for i.MX6SX open to other i.MX6x maybe not
a good choice, but we have runtime check.
Signed-off-by: Peng Fan <[email protected]>
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enable_spi_clock does the same thing with enable_cspi_clock, so
remove enable_cspi_clock.
Remove enable_cspi_clock prototype in header file
convert cm_fx6/spl.c to use enable_spi_clk
Signed-off-by: Peng Fan <[email protected]>
Acked-by: Stefano Babic <[email protected]>
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add I2C4 modul for MX6DL based boards.
Signed-off-by: Heiko Schocher <[email protected]>
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Add QSPI support for mx6solox.
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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mxc_get_clock's return type is unsigned int. 'return -1' is same with
'return 0xffffffff', so 0 should be used as the return value when
unsupported mxc_clock type is passed to mxc_get_clock.
Also include an err message when unsupported mxc_clock type is passed
to mxc_get_clock.
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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As checkpatch complaines about these camel-case defines, lets change
them to only use upper-case characters.
Signed-off-by: Stefan Roese <[email protected]>
Acked-by: Heiko Schocher <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Jon Nettleton <[email protected]>
Cc: Stefano Babic <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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Implement disable_sata_clock for mx6 SoCs.
Signed-off-by: Nikita Kiryanov <[email protected]>
Cc: Stefano Babic <[email protected]>
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Add api to check and enable pll3 as required
for thermal sensor driver.
Signed-off-by: Ye.Li <[email protected]>
Signed-off-by: Nitin Garg <[email protected]>
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For MX6SL and MX6SX, the perclk can come from OSC 24Mhz source. Fix
the get_ipg_per_clk function to support it.
Signed-off-by: Ye.Li <[email protected]>
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When CONFIG_SECURE_BOOT is enabled, the signed images
like kernel and dtb can be authenticated using iMX6 CAAM.
The added command hab_auth_img can be used for HAB
authentication of images. The command takes the image
DDR location, IVT (Image Vector Table) offset inside
image as parameters. Detailed info about signing images
can be found in Freescale AppNote AN4581.
Signed-off-by: Nitin Garg <[email protected]>
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Commit 224beb833e544b802f08765271cec07667d39669 add clock
enabling function for FEC, but the masks are not available
for SX processor and the mx6sxsabresd cannot be built clean.
Signed-off-by: Stefano Babic <[email protected]>
CC: Fabio Estevam <[email protected]>
CC: Nikita Kiryanov <[email protected]>
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Let PCI on mx6solox also be supported.
Signed-off-by: Fabio Estevam <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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Add functions to enable/disable clocks for UART, SPI, ENET, and MMC.
Cc: Stefano Babic <[email protected]>
Cc: Igor Grinberg <[email protected]>
Acked-by: Igor Grinberg <[email protected]>
Signed-off-by: Nikita Kiryanov <[email protected]>
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Configure and enable the ethernet clock for mx6solox.
Signed-off-by: Fabio Estevam <[email protected]>
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add enable_spi_clk(), so board code can enable spi clocks.
Signed-off-by: Heiko Schocher <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
Cc: Eric Nelson <[email protected]>
Cc: Stefano Babic <[email protected]>
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mx6sx does not have sata nor ipu blocks, so do not handle such clocks.
Signed-off-by: Fabio Estevam <[email protected]>
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mx6solox is the newest member of the mx6 family.
Some of the new features on this variants are:
- Cortex M4 microcontroller (besides the CortexA9)
- Dual Gigabit Ethernet
Add the initial support for it.
Signed-off-by: Fabio Estevam <[email protected]>
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DIV_SELECT is used as Fout = Fin * div_select / 2.0, so we should do
the shift after the multiply to avoid rounding errors
Signed-off-by: Andre Renaud <[email protected]>
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imx_get_fecclk() returns enet_ref instead of ipg.
Since the clock is used to calculate the prescaler
for the MDIO interface wrong values can be calculated.
Tested on a custom MX6S board with 100MBit interface
Signed-off-by: Markus Niebel <[email protected]>
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Split the SATA clock enabling function and add PCI express clock
enabling function. The SATA clock enabling function starts up the
100MHz SATA reference PLL in ENET_PLL register, but the code can
be re-used to enable the 125MHz PCIe reference in ENET_PLL, so pull
this code into separate function. Moreover, add the PCIe clock
enabling code.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Eric Nelson <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Stefano Babic <[email protected]>
Acked-by: Jagannadha Sutradharudu Teki <[email protected]>
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