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The configuration files imximage.cfg are used for the DDR controller
configuration.
Add DDR configuration function to replace the DDR controller
configuration in the imximage.cfg file. The function can be used for
DDR size detection.
Signed-off-by: Uri Mashiach <[email protected]>
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The CCM_ macros use the CCM_BASE_ADDRESS macro, which doesn't exist.
Replace the CCM_BASE_ADDRESS macros with CCM_BASE_ADDR.
Signed-off-by: Uri Mashiach <[email protected]>
Acked-by: Igor Grinberg <[email protected]>
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When compiling with W=1 the following warning is observed:
board/freescale/mx6sabresd/mx6sabresd.c:266:5: warning:
no previous prototype for ‘board_mmc_get_env_dev’
[-Wmissing-prototypes] int board_mmc_get_env_dev(int devno)
Remove this warning by adding the function prototype into sys_proto.h file.
Signed-off-by: Diego Dorta <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
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Add jump_to_image_linux() for arm64. Add "noreturn" flag to
armv8_switch_to_el2(). Add hooks to fsl-layerscape to enable falcon
boot.
Signed-off-by: York Sun <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Łukasz Majewski <[email protected]>
Tested-by: Łukasz Majewski <[email protected]>
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macro branch_if_master checks master CPU via (Aff3 & (Aff2:Aff1:Aff0))
it is simple but a little obscure.
fix by checking Affx fields within MPIDR_EL1 directly.
Signed-off-by: zijun_hu <[email protected]>
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U-Boot itself might need to identify the boot device, for example to be
able to tell where to load the kernel from when several options are
possible.
Move the logic of spl_boot_device to a function that is compiled both for
the SPL and the main binary.
Tested-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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The device model was implemented so far using a hook that needed to be
called from the board support, without DT support and only for the host.
Switch to probing both in peripheral and host mode through the DT.
Reviewed-by: Łukasz Majewski <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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Convert the arm architecture to make use of the new asm-generic/io.h to
provide address mapping functions. As the generic implementations are
suitable for arm this is primarily a matter of removing code.
This has only been build-tested, feedback from architecture maintainers
is welcome.
Signed-off-by: Paul Burton <[email protected]>
Cc: Albert Aribaud <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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The Rockchip BROM allows reading where it booted from from SRAM.
This adds the necessary definitions (as received from Kever) for
the location of this information in the RK3399's SRAM and naming
for the constants used.
Signed-off-by: Philipp Tomsich <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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configure_l2ctlr will be shared between SPL and TPL so
move them into asm/arch/sys_proto.h
Signed-off-by: Jagan Teki <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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L2CTLR read/write functions are common to armv7 so, move
them in to include/asm/armv7.h and use them where ever it need.
Cc: Tom Warren <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
[Backed out the change to arch/arm/mach-tegra/cache.c:]
Signed-off-by: Philipp Tomsich <[email protected]>
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Some of macros definition are not correct, fix them according to TRM.
Signed-off-by: Kever Yang <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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Add driver for rk322x to support sdram initialize in SPL.
Signed-off-by: Kever Yang <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.
Signed-off-by: David Wu <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.
Signed-off-by: David Wu <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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IFC code is put under CONFIG_FSL_IFC
Signed-off-by: Sriram Dash <[email protected]>
Reviewed-by: York Sun <[email protected]>
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This patch adds support for stm32h7 soc family, stm32h743
discovery and evaluation boards.
For more information about STM32H7 series, please visit:
http://www.st.com/en/microcontrollers/stm32h7-series.html
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This patch adds the ST glue logic to manage the DWC3 HC
on STiH407 SoC family. It configures the internal glue
logic and syscfg registers.
Part of this code been extracted from kernel.org driver
(drivers/usb/dwc3/dwc3-st.c)
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Unfortunately, the integrated macphy default is enabled, which will
increase power consuming, if we do not use this PHY. So let's disable
it at first, which will save power consuming. If we really use it, then
enable it in driver level.
Signed-off-by: David Wu <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
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Update these macros to use all upper-case to avoid checkpatch
warnings:
ENET_25MHz,
ENET_50MHz,
ENET_125MHz,
Signed-off-by: Eric Nelson <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
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This macro allows to detect whether the USB PHY is active. This
is helpful to detect if the boot ROM has previously started the
USB serial downloader.
The idea is taken from the mfgtool support in the NXP U-Boot:
http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/commit/?h=imx_v2016.03_4.1.15_2.0.0_ga&id=a352ed3c5184b95c4c9f7468f5fbb5f43de5e412
Signed-off-by: Stefan Agner <[email protected]>
Acked-by: Marcel Ziswiler <[email protected]>
Tested-by: Fabio Estevam <[email protected]>
Reviewed-by: Eric Nelson <[email protected]>
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Commit 6ae4c3efbd62 ("ARM: DRA7: Add pinctrl register definitions")
has added new macros for pinmux configuration in line with the kernel
definitions. Cleanup the old pinctrl macros from the common header
file so that they are not used by any new boards.
Signed-off-by: Suman Anna <[email protected]>
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DRA71x processors are reduced pin and software compatible
derivative of DRA72 processors. Add support for detection
of SR2.1 version of DRA71x family of processors.
Signed-off-by: Vishal Mahaveer <[email protected]>
Reviewed-by: Lokesh Vutla <[email protected]>
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Import include/linux/dma-direction.h from Linux 4.13-rc7 and delete
duplicated definitions of enum dma_data_direction.
Signed-off-by: Masahiro Yamada <[email protected]>
Reviewed-by: Andy Shevchenko <[email protected]>
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Add space around operator "+", make it
match the coding style.
Signed-off-by: Andy Yan <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Macro VA_BITS and PTE_BLOCK_BITS are not used
in the code, so remove them.
Signed-off-by: Andy Yan <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
Reviewed-by: York Sun <[email protected]>
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AM571x supports DDR running at 666MHz. Right now it is
clocked at 532MHz which is lower than what is supported.
In order to have maximum performance on AM571-IDK,
switch DDR to 666MHz.
Signed-off-by: Steve Kipisz <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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dra76-evm uses lp8736 and tps65917 pmic for powering on
various peripherals. Add data for these pmics and register
for dra76-evm.
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Keerthy <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
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dra76 family is a high-performance, infotainment application
device, based on OMAP architecture on a 28-nm technology.
This contains most of the subsystems, peripherals that are
available on dra74, dra72 family. This SoC mainly features
Subsystems:
- 2 x Cortex-A15 with max speed of 1.8GHz
- 2 X DSP
- 2 X Cortex-M4 IPU
- ISS
- CAL
- DSS
- VPE
- VIP
Connectivity peripherals:
- 1 USB3.0 and 3 USB2.0 subsystems
- 1 x SATA
- 2 x PCI Express Gen2
- 3-port Gigabit ethernet switch
- 2 x CAN
- MCAN
Adding CPU detection support for the dra76 ES1.0 soc
and update prcm, control module, dplls data.
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Praneeth Bajjuri <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
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It is not necessary all omap5+ based uses the same PMIC
to poweron mmc. So add support for enabling mmc based on board.
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
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The pcie config space of ls1088a is different from ls2080a.
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Rx Compliance tests may fail intermittently at high
jitter frequencies using default register values
Program register USB_PHY_RX_OVRD_IN_HI in certain sequence
to make the Rx compliance test pass.
Signed-off-by: Sriram Dash <[email protected]>
Signed-off-by: Rajesh Bhagat <[email protected]>
Signed-off-by: Suresh Gupta <[email protected]>
Signed-off-by: Ran Wang <[email protected]>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <[email protected]>
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Low Frequency Periodic Singaling (LFPS) Peak-to-Peak Differential
Output Voltage Test Compliance fails using default transmitter settings
Change config of transmitter signal swings by setting register
PCSTXSWINGFULL to 0x47 to pass compliance tests.
Signed-off-by: Sriram Dash <[email protected]>
Signed-off-by: Rajesh Bhagat <[email protected]>
Signed-off-by: Suresh Gupta <[email protected]>
Signed-off-by: Ran Wang <[email protected]>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <[email protected]>
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The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receive
Compliance test failure for a 100mV threshold.
Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE
to 0x0 to pass USB High Speed Receiver Sensitivity Compliance test.
Signed-off-by: Sriram Dash <[email protected]>
Signed-off-by: Rajesh Bhagat <[email protected]>
Signed-off-by: Suresh Gupta <[email protected]>
Signed-off-by: Ran Wang <[email protected]>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <[email protected]>
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USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature
Optimal eye at TXREFTUNE value to 0x9 is observed, change
set the same value.
Signed-off-by: Sriram Dash <[email protected]>
Signed-off-by: Suresh Gupta <[email protected]>
Signed-off-by: Ran Wang <[email protected]>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <[email protected]>
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Rx Compliance tests may fail intermittently at high
jitter frequencies using default register values.
Program register USB_PHY_RX_OVRD_IN_HI in certain sequence
to make the Rx compliance test pass.
Signed-off-by: Sriram Dash <[email protected]>
Signed-off-by: Rajesh Bhagat <[email protected]>
Signed-off-by: Suresh Gupta <[email protected]>
Signed-off-by: Ran Wang <[email protected]>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <[email protected]>
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Low Frequency Periodic Signaling(LFPS) Peak-to-Peak Differential
Output Voltage Test Compliance fails using default transmitter
settings
Change config of transmitter signal swings by setting register
PCSTXSWINGFULL to 0x47 to pass compliance tests.
Signed-off-by: Sriram Dash <[email protected]>
Signed-off-by: Rajesh Bhagat <[email protected]>
Signed-off-by: Suresh Gupta <[email protected]>
Signed-off-by: Ran Wang <[email protected]>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <[email protected]>
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The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receiver
Compliance test failure for a 100mV threshold.
Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE
to 0x0 to pass USB High Speed Receiver Sensitivity Compliance test.
Signed-off-by: Sriram Dash <[email protected]>
Signed-off-by: Rajesh Bhagat <[email protected]>
Signed-off-by: Suresh Gupta <[email protected]>
Signed-off-by: Ran Wang <[email protected]>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <[email protected]>
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USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature
Optimal eye at TXREFTUNE value to 0x9 is observed, change
set the same value.
Signed-off-by: Ran Wang <[email protected]>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <[email protected]>
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Some erratum patch might need it to program registers.
Signed-off-by: Ran Wang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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This patch adds support for RGMII protocol
NXP's LDPAA2 support RGMII protocol. LS1088A is the
first Soc supporting both RGMII and SGMII.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Signed-off-by: Amrita Kumari <[email protected]>
Signed-off-by: Ashish Kumar <[email protected]>
Reviewed-by: York Sun <[email protected]>
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LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.
Signed-off-by: Alison Wang <[email protected]>
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Signed-off-by: Ashish Kumar <[email protected]>
Signed-off-by: Raghav Dogra <[email protected]>
Signed-off-by: Shaohui Xie <[email protected]>
[YS: Revised commit message]
Reviewed-by: York Sun <[email protected]>
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For QSPI and IFC addresses execution shouldn't be allowed
when u-boot running from DDR. Revise the MMU final table
to enforce execute-never bits.
Signed-off-by: Suresh Gupta <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Adds header address for PPA to be validated during ESBC phase for
ARCH_LS2088 and QSPI_BOOT. Moves sec_init prior to ppa_init(). It
must be initialized before the PPA.
Signed-off-by: Udit Agarwal <[email protected]>
[YS: revised commit message]
Reviewed-by: York Sun <[email protected]>
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Unify memory map for Layerscape based platforms. This patch includes
changes in bootscript, bootscript header and PPA header addresses
change as per unified memory map.
Signed-off-by: Sumit Garg <[email protected]>
Tested-by: Vinitha Pillai <[email protected]>
Reviewed-by: York Sun <[email protected]>
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CoreLink Cache Coherent Interconnect (CCI) provides full cache
coherency between two clusters of multi-core CPUs and I/O coherency
for devices and I/O masters.
This patch add new config option SYS_FSL_HAS_CCI400 and moves
existing register space definaton of CCI-400 bus to fsl_immap to be
shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET
in Kconfig.
Signed-off-by: Ashish Kumar <[email protected]>
Signed-off-by: Prabhakar Kushwaha <[email protected]>
[YS: revised commit message, squashed patches for armv8 and armv7]
Reviewed-by: York Sun <[email protected]>
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Sometimes it's helpful to know the reset reason caused in the SoC.
Add reset reason detection for the RK3288 SoC.
This will set an environment variable which represents the reset reason.
Signed-off-by: Wadim Egorov <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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This converts the following to Kconfig:
CONFIG_SYS_I2C_BUS_MAX
Signed-off-by: Adam Ford <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
[trini: Fix AM43XX drop AM44XX]
Signed-off-by: Tom Rini <[email protected]>
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