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This patch renames the board directory from board/freescale to
board/nxp because NXP now provides Board Support Packages (BSPs) and
tools for the former Freescale i.MX and other i.MX products.
All relevant references have been updated accordingly. This change does
not affect functionality.
Signed-off-by: Alice Guo <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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Rename the variable and add ENV_ prefix, so that all configuration
options which are related to environment would have an CONFIG_ENV_
prefix. No functional change.
Use ENV_MMC_DEVICE_INDEX to clarify this is the SD/MMC device
index, a number, as enumerated by U-Boot. Update the help text
accordingly.
Signed-off-by: Marek Vasut <[email protected]>
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The decision on whether HAB is enabled is solely based on the SEC_CONFIG
fuse. The HAB FIELD_RETURN feature is able to permanently disable HAB on
a CPU, after which it is able to boot unsigned firmware. U-Boot however
does not take into account the FIELD_RETURN mode, and refuses to boot
unsigned software when the feature is enabled.
Also take the FIELD_RETURN fuse into account when deciding whether HAB
is enabled. When The FIELD_RETURN fuse is blown, HAB is not enabled.
Tested on i.MX8M Mini, i.MX8M Plus, i.MX8M Nano and i.MX6ULL
Signed-off-by: Paul Geurts <[email protected]>
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The imx_sec_config_fuse_t structure is not specific to the sec_config
fuse, but can be used for all fuse words.
Rename the structure to a more generic name to be reused for other
fuses.
Signed-off-by: Paul Geurts <[email protected]>
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Use the new symbol to refer to any 'SPL' build, including TPL and VPL
Signed-off-by: Simon Glass <[email protected]>
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Drop all duplicate newlines. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.
Reported-by: Jonas Karlman <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.
This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.
Reported-by: Jonas Karlman <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Remove <common.h> from all mach-imx, CPU specific sub-directories and
include/asm/arch-mx* files and when needed add missing include files
directly.
Acked-by: Peng Fan <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace.
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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SPL_GPIO_SUPPORT is named SPL_GPIO since commit 83061dbd1c89 ("Rename
GPIO_SUPPORT to GPIO"), SPL_MMC_SUPPORT is named SPL_MMC since commit
103c5f180694 ("mmc: Rename MMC_SUPPORT to MMC"), SPL_SERIAL_SUPPORT is
named SPL_SERIAL since commit 2a7360666871 ("serial: Rename
SERIAL_SUPPORT to SERIAL") so let's select the correct Kconfig options.
Fixes: 8b71576f3842 ("mx7ulp_com: add support for SPL")
Cc: Quentin Schulz <[email protected]>
Signed-off-by: Quentin Schulz <[email protected]>
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If probing caam_jr returns failure, the variable "dev" will not be
initialized, so we can't use dev->name for the error print.
Otherwise it will cause crash.
Signed-off-by: Ye Li <[email protected]>
Reviewed-by: Gaurav Jain <[email protected]>
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added crypto node in device tree.
sec is initialized based on job ring information processed
from device tree.
Signed-off-by: Gaurav Jain <[email protected]>
Reviewed-by: Ye Li <[email protected]>
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Similar to what has been done before with c5437e5b for u-boot proper, we
enable the SMP bit for SPL as well. This is necessary when SDP booting
straight into Linux, i.e. falcon boot. When SDP boot mode is active, the
ROM code does not set this bit which makes the caches not work once
activated in Linux.
On an i.MX6ULL (528MHz), this reduces a minimal kernel's boot time into
an initramfs shell from ~6.1s down to ~1.2s.
Signed-off-by: Sven Schwermer <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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Add EA iMX7ULP COM board support for building SPL.
Signed-off-by: Ricardo Salveti <[email protected]>
Signed-off-by: Oleksandr Suvorov <[email protected]>
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Force selecting features present in SoC i.MX7ULP.
Signed-off-by: Oleksandr Suvorov <[email protected]>
Reviewed-by: Igor Opaniuk <[email protected]>
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Get Unique ID of SoC iMX7ULP, using the logic described in Fusemap
(IMX7ULPRMB2_Rev0_Fusemap) attached in the i.MX 7ULP APRM [1].
[1]
https://www.nxp.com/docs/en/reference-manual/IMX7ULPRMB2.pdf
Signed-off-by: Ricardo Salveti <[email protected]>
Co-developed-by: Oleksandr Suvorov <[email protected]>
Signed-off-by: Oleksandr Suvorov <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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Update the mx7ulp wdog disable sequence to avoid potential reset
issue in unlock or refresh sequence. Both sequence need two words
write to wdog CNT register in 16 bus clocks window, if miss the
window, the write will cause violation in wdog and reset the chip.
Current u-boot code is using writel() function which has a DMB
barrier to order the memory access. The DMB between two words write
may introduce some delay in certain circumstance, causing the wdog
reset due to 16 bus clock window requirement.
Also, WDOG1 might have been enabled already depending on FUSE hence
we need to be as close as possible to its reconfiguration timing
requirement of 128 bus clock limit.
This patch replaces writel() function by __raw_writel() to avoid such
issue, and improve to check if watchdog is already disabled or
unlocked.
Signed-off-by: Ye Li <[email protected]>
Co-developed-by: Jorge Ramirez-Ortiz <[email protected]>
Signed-off-by: Jorge Ramirez-Ortiz <[email protected]>
Co-developed-by: Ricardo Salveti <[email protected]>
Signed-off-by: Ricardo Salveti <[email protected]>
Signed-off-by: Oleksandr Suvorov <[email protected]>
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Signed-off-by: Franck LENORMAND <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Historically, the reset_cpu() function had an `addr` parameter which was
meant to pass in an address of the reset vector location, where the CPU
should reset to. This feature is no longer used anywhere in U-Boot as
all reset_cpu() implementations now ignore the passed value. Generic
code has been added which always calls reset_cpu() with `0` which means
this feature can no longer be used easily anyway.
Over time, many implementations seem to have "misunderstood" the
existence of this parameter as a way to customize/parameterize the reset
(e.g. COLD vs WARM resets). As this is not properly supported, the
code will almost always not do what it is intended to (because all
call-sites just call reset_cpu() with 0).
To avoid confusion and to clean up the codebase from unused left-overs
of the past, remove the `addr` parameter entirely. Code which intends
to support different kinds of resets should be rewritten as a sysreset
driver instead.
This transformation was done with the following coccinelle patch:
@@
expression argvalue;
@@
- reset_cpu(argvalue)
+ reset_cpu()
@@
identifier argname;
type argtype;
@@
- reset_cpu(argtype argname)
+ reset_cpu(void)
{ ... }
Signed-off-by: Harald Seiler <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Move this out of the common header and include it only where needed. In
a number of cases this requires adding "struct udevice;" to avoid adding
another large header or in other cases replacing / adding missing header
files that had been pulled in, very indirectly. Finally, we have a few
cases where we did not need to include <asm/global_data.h> at all, so
remove that include.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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The command 'clocks' shows the following output:
=> clocks
PLL_A7_SPLL 528 MHz
PLL_A7_APLL 529 MHz
PLL_USB 0 MHz
Add some extra spaces so that the PLL_USB information gets aligned with
the previous reported frequencies.
Signed-off-by: Fabio Estevam <[email protected]>
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The command 'clocks' shows the following output:
=> clocks
PLL_A7_SPLL 528 MHz
PLL_A7_APLL 529 MHz
PLL_USB 0 MHz
....
[do_mx7_showclocks] addr = 0x9FFB61F1
The last line is not useful at all, so just remove it.
Signed-off-by: Fabio Estevam <[email protected]>
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Move this uncommon header out of the common header.
Signed-off-by: Simon Glass <[email protected]>
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Move this uncommon header out of the common header.
Signed-off-by: Simon Glass <[email protected]>
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Move this header out of the common header.
Signed-off-by: Simon Glass <[email protected]>
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We should not use typedefs in U-Boot. They cannot be used as forward
declarations which means that header files must include the full header to
access them.
Drop the typedef and rename the struct to remove the _s suffix which is
now not useful.
This requires quite a few header-file additions.
Signed-off-by: Simon Glass <[email protected]>
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It is bad practice to include common.h in other header files since it can
bring in any number of superfluous definitions. It implies that some C
files don't include it and thus may be missing CONFIG options that are set
up by that file. The C files should include these themselves.
Update some header files in arch/arm to drop this.
Signed-off-by: Simon Glass <[email protected]>
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LDO mode may be already enabled by the ROM and enabling it again
can cause U-Boot to hang.
Avoid this problem by only enabling LDO mode if it is initially disabled.
Reported-by: Jorge Ramirez-Ortiz <[email protected]>
Signed-off-by: Fabio Estevam <[email protected]>
Tested-by: Jorge Ramirez-Ortiz <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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These PMC0 definitions are already defined in the beginning
of the file, so remove the duplication.
Reported-by: Stefano Babic <[email protected]>
Signed-off-by: Fabio Estevam <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
---------------------------------
imx8: cleanup, fix warnings
imx6ull: add VisionSOM SoM and EVK
mx7ulp: fix warning due network, cleanup
mx7dsabre: Fix dm probe pmic
imx6: fixed for vining2000
Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/639512296
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On SPL enabled systems, the current s_init code (wdog, clock and ldo
init) is executed twice (by SPL and u-boot). This is not necessary and
might lead to boot issues (ie, starting PMC1 when it is already running).
Signed-off-by: Jorge Ramirez-Ortiz <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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Move this function out of common.h and into a relevant header file.
Signed-off-by: Simon Glass <[email protected]>
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These three clock functions don't use driver model and should be migrated.
In the meantime, create a new file to hold them.
Signed-off-by: Simon Glass <[email protected]>
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The Embedded Artists COM board is based on NXP i.MX7ULP.
It has a BD70528 PMIC from Rohm with discrete DCDC powering option and
improved current observability (compared to the existing NXP i.MX7ULP EVK).
Add the initial support for the board.
Signed-off-by: Fabio Estevam <[email protected]>
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scg_a7_apll_init() is not called anywhere, so remove such dead code
Signed-off-by: Fabio Estevam <[email protected]>
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The LDOVL definitions is common to all the modes, not only RUN mode,
so in order to avoid confusion, remove the _RUN notation from the PMC1
LDOVL definitions.
Signed-off-by: Fabio Estevam <[email protected]>
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Introduce the CONFIG_LDO_ENABLED_MODE option so that i.MX7ULP boards
designed to operate with LDO enabled mode can work with 0.95V at LDO
output in RUN mode as per the datasheet.
Signed-off-by: Fabio Estevam <[email protected]>
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As per the i.MX7ULP datasheet, it can boot in LDO enabled mode
or LDO bypass mode.
Print the LDO mode status in the U-Boot log for convenience.
Signed-off-by: Fabio Estevam <[email protected]>
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A number of board function belong in init.h with the others. Move them.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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CONFIG_SECURE_BOOT is too generic and forbids to use it for cross
architecture purposes. If Secure Boot is required for imx, this means to
enable and use the HAB processor in the soc.
Signed-off-by: Stefano Babic <[email protected]>
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On i.MX7ULP B0, there is change in NIC clock dividers architecture.
On A0, the NIC1 BUS and EXT dividers were in a chain with NIC1 DIV, but
on B0 they are parallel with NIC1 DIV. So now the dividers are independent.
This patch modifies the scg_nic_get_rate function according to this change.
Signed-off-by: Ye Li <[email protected]>
Acked-by: Peng Fan <[email protected]>
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The normal target frequency for ULP A7 core is 500Mhz, but now ROM
set the core frequency to 413Mhz. So change it to 500Mhz in u-boot.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Since there is no register for CPU revision, we use ROM version to
check the A0 or B0 chip.
Signed-off-by: Peng Fan <[email protected]>
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The GPU uses APLL PFD2 as its clock parent (483.84Mhz) with divider
set to 1. This frequecy is out of ULP A0 spec. The MAX rate for GPU
is 350Mhz. So we simply configure the APLL PFD2 to 345.6Mhz (FRAC=28)
to workaround the problem. The correct fix should let GPU handle the
clock rate in kernel.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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The num/denom is a float value, but in the calculation it is convert
to integer 0, and cause the result wrong.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Wrong I2c driver configuration name is used in codes, so I2c driver is
not built. Correct it.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Since many drivers need this CONFIG_MX7ULP to distiguish the settings
for i.MX7ULP only. Add this entry to cpu's kconfig.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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On i.MX7ULP, value zero is reserved in SCG1 RCCR register,
so the val should be decreased by 1 to get the correct clock
source index.
Signed-off-by: Bai Ping <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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The board will reboot if A7 core enter mem mode by rtc, then M4 core
enter VLLS mode after the RTC alarm expired. Enable the dumb PMIC mode
to fix this issue.
Since i.MX7ULP B0 moves the SNVS LP into M4 domain, A core can't access
it. So check the CPU rev and not apply the settings for B0.
Signed-off-by: Bai Ping <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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