| Age | Commit message (Expand) | Author |
|---|---|---|
| 2023-07-24 | riscv: define a cache line size for the generic CPU | Heinrich Schuchardt |
| 2023-07-12 | riscv: Rename SiFive CLINT to RISC-V ALINT | Bin Meng |
| 2021-05-19 | riscv: qemu: Switch to use binman to generate u-boot.itb | Bin Meng |
| 2021-05-17 | riscv: Split SiFive CLINT support between SPL and U-Boot proper | Bin Meng |
| 2021-03-27 | cpu: Rename SPL_CPU_SUPPORT to SPL_CPU | Simon Glass |
| 2020-09-30 | riscv: Rework riscv timer driver to only support S-mode | Sean Anderson |
| 2019-08-26 | riscv: add SPL support | Lukas Auer |
| 2019-08-26 | riscv: add run mode configuration for SPL | Lukas Auer |
| 2019-02-27 | riscv: Rename cpu/qemu to cpu/generic | Anup Patel |
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index : u-boot.git | |
| Unnamed repository; edit this file 'description' to name the repository. |
| summaryrefslogtreecommitdiff |