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Under single core boot platform, the secondary cores won't enter the
u-boot spl. Therefore we move the pl2 driver from u-boot to the Opensbi.
Signed-off-by: Nick Hu <[email protected]>
Signed-off-by: Jimmy Ho <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Use the new symbol to refer to any 'SPL' build, including TPL and VPL
Signed-off-by: Simon Glass <[email protected]>
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The power gating feature of pl2 should be enabled as early as possible,
it would be better to put it in SPL stage.
Signed-off-by: Zong Li <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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We can remove common.h from most cases of the code here, and only a few
places need an additional header instead.
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
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The enable_caches is a generic hook for architecture-implemented, we
define this function to enable composable cache of sifive platforms.
In sifive_cache, it invokes the generic cache_enable interface of cache
uclass to execute the relative implementation in SiFive ccache driver.
Signed-off-by: Zong Li <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
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