summaryrefslogtreecommitdiff
path: root/board/phytec/phycore_am62x
AgeCommit message (Collapse)Author
2026-03-13Merge patch series "board: k3: Sync rm-cfg with TIFS v11.02.09 firmware"Tom Rini
Sparsh Kumar <[email protected]> says: This series updates the Resource Management (RM) configuration files for AM62 family devices to align with the TIFS v11.02.09 firmware. Background ---------- With the latest TIFS firmware (v11.02.09), an additional virtual interrupt and event is reserved for MCU cores to DM usage on am62x, am62ax, and am62px devices. This series brings the rm-cfg and tifs-rm-cfg files in sync with these firmware changes across both TI reference boards and vendor boards. These changes are backward compatible with older TIFS firmware versions. Additionally, the am62x platform was originally introduced without a tifs-rm-cfg.yaml file, unlike other platforms in the AM62 family. This series addresses that gap and enables tifs-rm-cfg in binman for am625-sk and am62p-sk platforms. Changes ------- TI reference boards (patches 1-4): - Update rm-cfg.yaml for am62x, am62ax, am62px - Sync am62px tifs-rm-cfg.yaml with TIFS firmware template - Add missing tifs-rm-cfg.yaml for am62x - Enable tifs-rm-cfg in binman for am625-sk and am62p-sk Vendor boards (patches 5-9): - beagleplay (am62x-based) - phytec phycore_am62x - toradex verdin-am62 - phytec phycore_am62ax - toradex verdin-am62p with the required interrupt reservation. The tifs-rm-cfg.yaml files cannot be updated without access to the corresponding SysConfig files, as both rm-cfg.yaml and tifs-rm-cfg.yaml must remain in sync. Link: https://lore.kernel.org/r/[email protected]
2026-03-13board: phytec: rm-cfg: Update rm-cfg to reflect new resource reservationSparsh Kumar
With the latest v11.02.09 TIFS firmware, an additional virtual interrupt and event is reserved for MCU cores to DM usage on am62x devices. Update the rm-cfg to reflect this new reservation. Signed-off-by: Sparsh Kumar <[email protected]>
2026-02-23board: Correct usage of fdtfile=CONFIG_DEFAULT_FDT_FILETom Rini
As explained in commit 03d2d5fc003f ("board: sifive: unmatched: set fdtfile with unquoted variable.") using the syntax of 'fdtfile=CONFIG_DEFAULT_FDT_FILE' in the plain text environment files will lead to extraneous and problematic "s in the output. This is fixed by using fdtfile=DEFAULT_FDT_FILE which was introduced recently. Acked-by: Peng Fan <[email protected]> Signed-off-by: Tom Rini <[email protected]>
2026-01-21board: phytec: Add PHYTEC mailing list to MAINTAINERS entriesWadim Egorov
PHYTEC maintains an actively monitored mailing list for upstream activities: [email protected]. Add it to the MAINTAINERS entries for PHYTEC boards we actively develop and contribute to. Signed-off-by: Wadim Egorov <[email protected]> Acked-by: Teresa Remmet <[email protected]>
2025-10-22spl: split spl_board_fixups to arch/board specificAnshul Dalal
The current spl_board_fixups API allows for modification of spl_image before the SPL jumps to it. This can be used to modify the DT for the next boot stage, however the current API only allows either the machine arch or the board to use it. This limits the utility of the API as there might be certain fixups that should be applied to all boards sharing the same machine architecture with others being board specific. For TI's K3 specifically, this prevents us from performing architecture level fixups since a lot of TI boards are already making use of the spl_board_fixups API. Therefore this patch splits the API into two to allow both board and the architecture specific fixups. The order is kept as arch then board to give board specific fixups the precedence. Reviewed-by: Dhruva Gole <[email protected]> Signed-off-by: Anshul Dalal <[email protected]> Tested-by: Wadim Egorov <[email protected]>
2025-09-30Merge tag 'u-boot-socfpga-next-20250930' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-socfpga into next SoCFPGA updates for v2025.10: CI: https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/27762 This pull request brings a set of updates across SoCFPGA platforms covering Agilex5, Agilex7, N5X, and Stratix10. The changes include: * Agilex5 enhancements: - USB3.1 enablement and DWC3 host driver support - System Manager register configuration for USB3 - Watchdog timeout increase and SDMMC clock API integration - dcache handling improvements in SMC mailbox path - Enable SPL_SYS_DCACHE_OFF in defconfig * Clock driver improvements: - Introduce dt-bindings header for Agilex clocks - Add enable/disable API and EMAC clock selection fixes - Replace manual shifts with FIELD_GET usage * DDR updates: - IOSSM mailbox compatibility check - Correct DDR calibration status handling * Device tree changes: - Agilex5: disable cache allocation for reads - Stratix10: add NAND IP node - Enable driver model watchdog - Enable USB3.1 node for Agilex5 * Config cleanups: - Simplify Agilex7 VAB defconfig - Remove obsolete SYS_BOOTM_LEN from N5X VAB config - Enable CRC32 support for SoCFPGA - Increase USB hub debounce timeout Overall this set improves reliability of DDR and cache flows, adds missing USB and MMC features for Agilex5, and refines clock and configuration handling across platforms. This patch set has been tested on Agilex 5 devkit, and Agilex devkit.
2025-09-24board: phytec: phycore_am6xx: Update scriptaddrWadim Egorov
After switching our boards to standard boot, we observed that the kernel hangs when booting with the "script" boot method over the network. The original scriptaddr value was copied from ti_common.env and remained unused for some time. On phycore-am62x and phycore-am62ax, however, this address conflicts with the current location where ATF is loaded (CONFIG_K3_ATF_LOAD_ADDR). Move scriptaddr to 0x89100000, directly after fdtoverlay_addr_r. The phycore-am64x is not affected by this issue, but we update it as well to keep all phycore-am6xx boards consistent. Signed-off-by: Wadim Egorov <[email protected]> Reviewed-by: Anshul Dalal <[email protected]>
2025-08-25Merge tag 'v2025.10-rc3' into nextTom Rini
Prepare v2025.10-rc3
2025-08-25board: phytec: phycore_am6xx: Add rauc to bootmethsWadim Egorov
Add rauc to bootmeths variable if BOOTMETH_RAUC is enabled. This is setting a proper default for RAUC enabled systems. Signed-off-by: Wadim Egorov <[email protected]> Reviewed-by: Martin Schwan <[email protected]>
2025-08-11board: phytec: phycore-am62x: Add watchdog start to bootcmdWadim Egorov
Allows run-time control over watchdog auto-start and the timeout via setting the environment variable watchdog_timeout_ms. A value of zero means "do not start". Use CONFIG_WATCHDOG_TIMEOUT_MSECS as initial value. Users can enable the watchdog to monitor the boot process until userspace or OS takes over to serve the watchdog. Signed-off-by: Wadim Egorov <[email protected]>
2025-07-24treewide: Remove empty board_init() function from all boardsSam Protsenko
Commit 86acdce2ba88 ("common: add config for board_init() call") introduced CONFIG_BOARD_INIT option. This option can be disabled for the boards where board_init() function is not needed. Remove empty board_init() calls for all boards where it's possible, and disable CONFIG_BOARD_INIT in all related defconfigs. This cleanup was made semi-automatically using these scripts: [1]. No functional change, but the binary size for the modified boards is reduced a bit. [1] https://github.com/joe-skb7/uboot-convert-scripts/tree/master/remove-board-init Signed-off-by: Sam Protsenko <[email protected]> Tested-by: Adam Ford <[email protected]> #imx8mm_beacon Tested-by: Bryan Brattlof <[email protected]> Acked-by: Peng Fan <[email protected]> #NXP boards
2025-07-08board: phytec: rm-cfg: Update rm-cfg to reflect new resource reservationWadim Egorov
With the latest TIFS firmware, an additional virtual interrupt and event is reserved for TIFS usage on am62x and am62ax devices. Update the rm-cfg to reflect this new reservation. Based on commit 87720385ab69 ("board: ti: rm-cfg: Update rm-cfg to reflect new resource reservation"). Signed-off-by: Wadim Egorov <[email protected]>
2025-05-22board: phytec: phycore_am6xx: Set bootmeths & boot_targets environmentWadim Egorov
As part of our migration to the standard boot process, configure the default values for the bootmeths and boot_targets environment variables. Signed-off-by: Wadim Egorov <[email protected]>
2025-05-22board: phytec: phycore_am62x: Update environment for fitbootNathan Morrisson
Add fit_addr_r to the environment to allow us to boot from a FIT image. Signed-off-by: Nathan Morrisson <[email protected]> Signed-off-by: Wadim Egorov <[email protected]>
2025-05-09board: ti: sec-cfg.yaml: Fix OTP write_host_id orderAndrew Davis
The write_host_id is the last element here and order does matter. This may have gone unnoticed before as by default all elements are 0, but if this is updated to a different host, it will not work. Update the order so write_host_id is the last element in all current secure board configs. Reported-by: Prashant Shivhare <[email protected]> Signed-off-by: Andrew Davis <[email protected]>
2025-04-10Merge patch series "*** Add Ethernet boot support for AM62Ax + phyCORE-AM62 ↵Tom Rini
SoMs ***" Wadim Egorov <[email protected]> says: Add general ethernet boot support for AM62Ax SoC. Some of the work is based on TI's downstream u-boot patches found in [1], patches touching code in mach-k3 and *.yaml board config files. Also, provide defconfigs and device tree changes for phyCORE-AM62x and phyCORE-AM62Ax to support booting via ethernet. [1] https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1307981/sk-am62a-lp-rgmii-boot-mode-problem Link: https://lore.kernel.org/r/[email protected]
2025-04-10configs: Add phycore_am62x_r5_ethboot_defconfigWadim Egorov
Provide a defconfig for booting the phycore-am62x via Ethernet. We need a separate defconfig because the AM62x has not enough internal SRAM to support all boot sources. Signed-off-by: Wadim Egorov <[email protected]>
2025-03-18Merge patch series "*** Various Improvements for phyCORE-AM62/A SoMs ***"Tom Rini
Wadim Egorov <[email protected]> says: This patch series syncs the phyCORE-AM62Ax feature-wise with our other K3-based SoMs by adding SoM overlay handling and capsule updates. It also introduces support for USBDFU boot and includes various minor fixes. Link: https://lore.kernel.org/r/[email protected]
2025-03-18board: phytec: phycore_am62x: Use custom k3_dfu.env fragmentWadim Egorov
TI's k3_dfu.env includes redundant dfu_alt_info_* data, some of which is incompatible with our board configuration. Replace it with a custom variant that better aligns with our setup, ensuring correct offsets and eliminating unnecessary entries. Signed-off-by: Wadim Egorov <[email protected]>
2025-03-18doc: phytec: k3: Add a common part for Environment and EFI CapsulesWadim Egorov
Provide a common part for our K3 based boards including general details about environment handling and EFI capsule updates. Signed-off-by: Wadim Egorov <[email protected]>
2025-02-20board: Phytec: phycore_am62x: Increase size for Image in SPIDaniel Schultz
Increase the maximum Image size from 23 MB to 26 MB by moving the initramfs start address up. This gives us a bigger ranger to provide kernel images which are not stripped down too much. Signed-off-by: Daniel Schultz <[email protected]> Reviewed-by: Wadim Egorov <[email protected]>
2025-01-23board: phytec: phycore-am62x: Add DDR size fixups if ECC is enabledWadim Egorov
With commit 22ce56a3ebdb ("ram: k3-ddrss: Add k3_ddrss_ddr_bank_base_size_calc() to solve 'calculations restricted to 32 bits' issue") we need to provide the detected RAM size in the device tree node prio to K3 DDRSS driver probe. This is done by calling fdt_fixup_memory_banks() in do_board_detect(). After probing, call into k3-ddrss driver to fixup device tree and resize the available amount of DDR if ECC is enabled. A third fixup is required from A53 SPL to take the fixup as done from R5 SPL and apply it to DT passed to A53 U-boot, which in turn passes this to the OS. Signed-off-by: Wadim Egorov <[email protected]>
2024-12-04board: phytec: common: Introduce CONFIG_PHYTEC_K3_DDR_PATCHGarrett Giordano
Introduce CONFIG_PHYTEC_K3_DDR_PATCH to make DDR timing patch code optional for PHYTEC K3 boards. This allows better control over which boards receive DDR timing patches, rather than compiling the code for all boards with K3_DDRSS enabled. Also enable the feature by default for PHYCORE_AM62X_R5. Signed-off-by: Garrett Giordano <[email protected]> Reviewed-by: Wadim Egorov <[email protected]>
2024-10-11board: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILDSimon Glass
Use the new symbol to refer to any 'SPL' build, including TPL and VPL Signed-off-by: Simon Glass <[email protected]>
2024-09-10Merge patch series "phycore-am62/4: Add more boot sources"Tom Rini
Daniel Schultz <[email protected]> says: This patch stack extends the phyCORE-AM62x/AM64x U-Boot by following boot sources: - Load U-Boot with USB DFU - Load a Linux and initramfs from OSPI/QSPI NOR flash - Load a Linux and rootfs from Network Moreover, it adds required changes to the environment to boot an A/B system with RAUC and includes some minor fixes.
2024-09-10board: phytec: phycore_am62x: Add Network/SPI BootDaniel Schultz
Include the boot logic to boot via Network or from a OSPI/QSPI NOR flash. Moreover, set all required variables to both boot methods to the environment. Signed-off-by: Daniel Schultz <[email protected]>
2024-07-22board: phytec: phycore_am62x: Use k3_mmc.env logicDaniel Schultz
Use our common environment file to implement MMC boot. Signed-off-by: Daniel Schultz <[email protected]> Reviewed-by: Dhruva Gole <[email protected]> Reviewed-by: Wadim Egorov <[email protected]>
2024-07-16board: phytec: phycore_am62x: Move earlycon into own variableDaniel Schultz
By moving the earlycon definition into a dedicated variable, it's easier to change these values in case the kernel should print on a different serial interface. Signed-off-by: Daniel Schultz <[email protected]>
2024-06-18board: phytec: phycore-am62x: Use memory nodes in higher boot stagesWadim Egorov
There is no need to reread the EEPROM multiple times in different stages to detect the RAM size. We can do this once at an early stage and let higher stages decode memory nodes using fdtdec. Make sure to pass fixup memory nodes before passing to u-boot stage. Signed-off-by: Wadim Egorov <[email protected]> Reviewed-by: Daniel Schultz <[email protected]>
2024-06-18board: phytec: phycore-am62x: Pull in k3_dfu.envWadim Egorov
Pull in ti/k3_dfu.env for dfu_alt_info_ram in SPL stage. Signed-off-by: Wadim Egorov <[email protected]> Reviewed-by: Daniel Schultz <[email protected]>
2024-06-18board: phytec: phycore-am62x: Fix CONFIG_SPL_BOARD_INITWadim Egorov
Make sure spl_board_init() gets compiled by enabling missing CONFIG_SPL_BOARD_INIT and including hardware.h. Fixes: 085cd6459dae ("board: phytec: am62x: Add PHYTEC phyCORE-AM62x SoM") Signed-off-by: Wadim Egorov <[email protected]> Reviewed-by: Daniel Schultz <[email protected]>
2024-06-07board: phytec: am62x: Add support for 1 & 4 GB RAM variantsWadim Egorov
Use content of EEPROM to detect the actual RAM size and adjust DDR timings, size and banks accordingly. Also enable the SoM detection per default in the defconfigs. Signed-off-by: Wadim Egorov <[email protected]> Tested-by: John Ma <[email protected]>
2024-06-07board: phytec: common: Introduce a method to inject DDR timings deltasWadim Egorov
Introduce fdt_apply_ddrss_timings_patch() to allow board code to override DDR settings in the device tree prior to DDRSS driver probing. Signed-off-by: Wadim Egorov <[email protected]> Tested-by: John Ma <[email protected]>
2024-05-10Merge patch series "*** Commonize board code for K3 based SoMs ***"Tom Rini
Wadim Egorov <[email protected]> says: Factor out code that we can reuse across all our K3 based SoMs. 2nd patch of this series require patch [1] to be applied first. [1] https://lists.denx.de/pipermail/u-boot/2024-April/552021.html
2024-05-10board: phytec: Commonize board code for K3 based SoMsWadim Egorov
Environment handling code can be reused across all our K3 based SoMs. Instead of adding the same code for every new SoM, move it to a common board.c file. Signed-off-by: Wadim Egorov <[email protected]>
2024-04-29Merge patch series "Update PHYTEC SOM Detection"Tom Rini
Daniel Schultz <[email protected]> says: This patch series extends PHYTEC's SOM detection by minor fixes, a generic helper function and a new valid flag. Moreover, it adds a module to provide access to the SOM detection for our TI AM6 products.
2024-04-29board: phytec: Add SOM detection for AM6xDaniel Schultz
Add all functions to read each SOM option from the EEPROM image and detect whether it's the correct product for this image. Signed-off-by: Daniel Schultz <[email protected]>
2024-04-29phycore-am62x: Migrate to OF_UPSTREAMWadim Egorov
The phycore-am62x can be migrated to OF_UPSTREAM. Drop redundant device tree files, update MAINTAINERS and defconfig's DEFAULT_DEVICE_TREE for ti vendor prefix accordingly. Signed-off-by: Wadim Egorov <[email protected]>
2024-04-11board: phycore-am62x: Extend for better environment handlingWadim Egorov
Select environment location based on the device we boot from. Also, introduce a "boot" variable that represents the current boot device and can be used by scripts. Signed-off-by: Wadim Egorov <[email protected]>
2024-01-18board: ti: *-cfg.yaml: Adhere to yamllint rulesNeha Malcom Francis
Clean up all configuration files to adhere to yamllint rules. Signed-off-by: Neha Malcom Francis <[email protected]> [trini: Update more yaml files added since this was posted] Signed-off-by: Tom Rini <[email protected]> Suggested-by: Nishanth Menon <[email protected]>
2024-01-16board: phytec: am62x: Add PHYTEC phyCORE-AM62x SoMWadim Egorov
Add basic support for PHYTEC phyCORE-AM62x SoM. Supported features: - 2GB DDR4 RAM - eMMC Flash - OSPI NOR Flash - external uSD - Ethernet - debug UART Product page SoM: https://www.phytec.com/product/phycore-am62x Device trees were taken from Linux v6.7-rc3. Signed-off-by: Wadim Egorov <[email protected]> Reviewed-by: Dhruva Gole <[email protected]>