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TARGET namespace is for machines / boards / what-have-you that
building U-Boot for. Simply replace from TARGET to ARCH
make things more clear and proper for ALL SoCFPGA.
Signed-off-by: Brian Sune <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
# Conflicts:
# drivers/ddr/altera/Makefile
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Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex.
Signed-off-by: Siew Chin Lim <[email protected]>
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Add SDRAM driver for Agilex SoC.
Signed-off-by: Tien Fong Chee <[email protected]>
Signed-off-by: Ley Foon Tan <[email protected]>
Reviewed-by: Simon Goldschmidt <[email protected]>
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Convert Stratix 10 SDRAM driver to device model.
Get rid of call to socfpga_per_reset() and use reset
framework.
SPL is changed from calling function in SDRAM driver
directly to just probing UCLASS_RAM.
Move sdram_s10.h from arch to driver/ddr/altera directory.
Signed-off-by: Ley Foon Tan <[email protected]>
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Compile ALTERA_SDRAM driver in SPL only.
Rename ALTERA_SDRAM to SPL_ALTERA_SDRAM.
Signed-off-by: Ley Foon Tan <[email protected]>
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To clean up reset handling for socfpga gen5, port the DDR driver to DM
using UCLASS_RAM and implement proper reset handling.
This gets us rid of one ad-hoc call to socfpga_per_reset().
The gen5 driver is implemented in 2 distinct files. One of it (containing
the calibration training) is not touched much and is kept at using
hard coded addresses since the code grows even more otherwise.
SPL is changed from calling hard into the DDR driver code to just
probing UCLASS_RESET and UCLASS_RAM. It is happy after finding a RAM
driver after that.
Signed-off-by: Simon Goldschmidt <[email protected]>
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This patch enables DDR Kconfig support for Arria 10.
Signed-off-by: Tien Fong Chee <[email protected]>
Reviewed-by: Dinh Nguyen <[email protected]>
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Convert Altera DDR SDRAM driver to use Kconfig method.
Enable ALTERA_SDRAM by default if it is on Gen5 target.
Arria 10 will have different driver.
Signed-off-by: Tien Fong Chee <[email protected]>
Signed-off-by: Ley Foon Tan <[email protected]>
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