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Drop all duplicate newlines. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.
Reported-by: Jonas Karlman <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.
This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.
Reported-by: Jonas Karlman <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Remove <common.h> from this driver directory and when needed
add missing include files directly.
Signed-off-by: Tom Rini <[email protected]>
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The KBUILD_BASENAME contains just the name of the compiled module,
in this case 'sequencer', rather than a full path to the compiled
file. Use it to prevent pulling the full path into the U-Boot binary,
which is useless and annoying.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Siew Chin Lim <[email protected]>
Cc: Simon Goldschmidt <[email protected]>
Cc: Tien Fong Chee <[email protected]>
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The values of left_edge[0] and right_edge[0] are overwritten before they
are used. Remove the superfluous assignments.
Fixes: 285b3cb939a8 ("dm: ddr: socfpga: fix gen5 ddr driver to not use bss")
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Move this header out of the common header.
Signed-off-by: Simon Glass <[email protected]>
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Add DDR2 support to Gen5 DRAM driver. As the DDR2 macro names generated
by Quartus are named differently than the DDR3 ones, use anon unions to
store them in the same structures, without growing their size.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Ley Foon Tan <[email protected]>
Cc: Simon Goldschmidt <[email protected]>
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This driver uses bss from SPL board_init_f(). Change it to move all the
data from bss to a common struct allocated on the stack (64 byte).
In addition to saving 28 bytes of bss, the code even gets 264 bytes
smaller.
Signed-off-by: Simon Goldschmidt <[email protected]>
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To clean up reset handling for socfpga gen5, port the DDR driver to DM
using UCLASS_RAM and implement proper reset handling.
This gets us rid of one ad-hoc call to socfpga_per_reset().
The gen5 driver is implemented in 2 distinct files. One of it (containing
the calibration training) is not touched much and is kept at using
hard coded addresses since the code grows even more otherwise.
SPL is changed from calling hard into the DDR driver code to just
probing UCLASS_RESET and UCLASS_RAM. It is happy after finding a RAM
driver after that.
Signed-off-by: Simon Goldschmidt <[email protected]>
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When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.
In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.
This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.
Signed-off-by: Tom Rini <[email protected]>
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This driver has been using printf() including filename since it was
added. Convert to using debug() instead.
Signed-off-by: Simon Goldschmidt <[email protected]>
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The code uses a lot of signed numbers, which ended up in variables
of unsigned type, which resulted in all sorts of underflows. This
in turn caused incorrect calibration on certain boards. Moreover,
repair the readout of the DQ delay, which was being pulled from
wrong register.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Chin Liang See <[email protected]>
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Just staticize global variables in sequencer, since there is no
point in having these symbols available outside of the DDR code.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Chin Liang See <[email protected]>
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Originally, the DLEVEL selects the debug level within the sequencer code,
but only displays the messages on that particular debug level. Tweak the
handling such that for particular debug level, debug messages on that
level and lower are displayed. This allows better regulation of debug
message verbosity.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Chin Liang See <[email protected]>
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This one last set of delay configuration registers was not properly
zeroed out originally, fix it and zero them out.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Chin Liang See <[email protected]>
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There is no point in resetting the ODT setting if the write test
failed, since the code will always retry the calibration and thus
reconfigure the ODT anyway OR the code will fail calibration and
halt.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Chin Liang See <[email protected]>
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Every invocation of the scc_mgr_set_dqs_en_delay_all_ranks() is
followed by SCC manager update. Moreover, only this function
triggers the SCC manager update internally. Thus, remove the
internal invocation to avoid triggering the update twice.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Chin Liang See <[email protected]>
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The code should be setting registers to zero, not one register to value.
Swap the order of arguments to correct the behavior. The behavior is now
in-line with code generated by Quartus 15.1 .
Signed-off-by: Marek Vasut <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Chin Liang See <[email protected]>
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In the most unlikely case the DQS tracking was to be disabled,
make sure we do not errornously re-enable it. Note that DQS
tracking is enabled on all systems observed thus far.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Chin Liang See <[email protected]>
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The bit 22 is in fact DQS tracking enable bit (dqstrken) and there
is a macro for this bit already, so use it.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Chin Liang See <[email protected]>
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Fix the following problem:
drivers/ddr/altera/sequencer.c: In function 'sdram_calibration_full':
drivers/ddr/altera/sequencer.c:1943:25: warning: 'found_failing_read' may be used uninitialized in this function [-Wmaybe-uninitialized]
if (found_passing_read && found_failing_read)
^
drivers/ddr/altera/sequencer.c:1803:26: note: 'found_failing_read' was declared here
u32 found_passing_read, found_failing_read, initial_failing_dtap;
^
Signed-off-by: Marek Vasut <[email protected]>
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This gem is really really rare, there was an actual float used in
the Altera DDR init code, which pulled in floating point ops from
the libgcc, just wow.
Since we don't support floating point operations the same way Linux
does not support them, replace this with an integer multiplication
and division combo. This removes some 2kiB of size from the SPL as
the floating point ops are no longer pulled in from libgcc.
This was detected by enabling CONFIG_USE_PRIVATE_LIBGCC=y , which
does not contain the floating point bits.
Signed-off-by: Marek Vasut <[email protected]>
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Fix most of the dangling checkpatch issues, no functional change.
There are still 7 warnings, 1 checks , but those are left in place
for the sake of readability of the code.
Signed-off-by: Marek Vasut <[email protected]>
Acked-by: Dinh Nguyen <[email protected]>
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Replace uintNN_t with uNN. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
Acked-by: Dinh Nguyen <[email protected]>
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Actually convert the sequencer code to use socfpga_sdram_misc_config
instead of the various macros. This is just an sed exercise here, no
manual coding needed.
This patch actually removes the need to include any board-specific
files in sequencer.c , so sequencer.c namespace is now no longer
poluted by QTS-generated macros.
Signed-off-by: Marek Vasut <[email protected]>
Acked-by: Dinh Nguyen <[email protected]>
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This is another macro used to obfuscate the real code. The
T(INIT|RESET)_CNTR._VAL is always defined, so this indirection
is unnecessary. Get rid of this.
Signed-off-by: Marek Vasut <[email protected]>
Acked-by: Dinh Nguyen <[email protected]>
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Just use READ_VALID_FIFO_SIZE directly, no need for this macro obfuscation.
Signed-off-by: Marek Vasut <[email protected]>
Acked-by: Dinh Nguyen <[email protected]>
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Introduce structure socfpga_sdram_misc_config to wrap the remaining
misc configuration values in board file. Again, introduce a function,
socfpga_get_sdram_misc_config(), which returns this the structure. This
is almost the final step toward wrapping the nasty QTS generated macros
in board files and reducing the pollution of the namespace.
Signed-off-by: Marek Vasut <[email protected]>
Acked-by: Dinh Nguyen <[email protected]>
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Actually convert the sequencer code to use socfpga_sdram_io_config
instead of the IO_* macros. This is just an sed excercise here, no
manual coding needed.
Signed-off-by: Marek Vasut <[email protected]>
Acked-by: Dinh Nguyen <[email protected]>
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Introduce structure socfpga_sdram_io_config to wrap the IO configuration
values in board file. Introduce socfpga_get_sdram_io_config() function,
which returns this the structure. This is another step toward wrapping
the nasty QTS generated macros in board files and reducing the pollution
of the namespace.
Signed-off-by: Marek Vasut <[email protected]>
Acked-by: Dinh Nguyen <[email protected]>
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Actually convert the sequencer code to use socfpga_sdram_rw_mgr_config
instead of the RW_MGR_* macros. This is just an sed exercise here, no
manual coding needed.
Signed-off-by: Marek Vasut <[email protected]>
Acked-by: Dinh Nguyen <[email protected]>
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Introduce structure socfpga_sdram_rw_mgr_config to wrap the RW manager
configuration values in board file. Introduce a complementary function,
socfpga_get_sdram_rwmgr_config(), which returns this the structure.
This is another step toward wrapping the nasty QTS generated macros
in board files and reducing the pollution of the namespace.
Signed-off-by: Marek Vasut <[email protected]>
Acked-by: Dinh Nguyen <[email protected]>
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Introduce two wrapper functions, socfpga_get_seq_ac_init() and
socfpga_get_seq_inst_init() to avoid direct inclusion of the
sequencer_auto_ac_init.h and sequencer_auto_inst_init.h QTS
generated files. This reduces namespace pollution again.
Signed-off-by: Marek Vasut <[email protected]>
Acked-by: Dinh Nguyen <[email protected]>
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These parameters are not used in the code, zap them and the
macros which are used by them as well.
Signed-off-by: Marek Vasut <[email protected]>
Acked-by: Dinh Nguyen <[email protected]>
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Move the files generated by QTS into the board directory, they should not
be part of the driver files at all.
Signed-off-by: Marek Vasut <[email protected]>
Acked-by: Dinh Nguyen <[email protected]>
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Add kerneldoc.
Signed-off-by: Marek Vasut <[email protected]>
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Simplify the loop code, optimizing compiler can deal with this.
No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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Clean up the computation of c_loop, outer and inner variables.
Signed-off-by: Marek Vasut <[email protected]>
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Factor out (afi_clocks - 1) into a single place instead of having it
all around the function.
Signed-off-by: Marek Vasut <[email protected]>
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Fix data types, clean up comments a bit and fix coding style a bit.
No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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Add kerneldoc and perform a minor comment cleanup.
Signed-off-by: Marek Vasut <[email protected]>
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Minor coding style cleanup, add kerneldoc. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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This function is implementing the DDR calibration Stage 3 as
described in Altera EMI_RM 2015.05.04 . The main body of this
function is almost identical to Stage 1.3 (DQ/DQS centering)
for all but two flags -- use_read_test and update_fom. Convert
this function to call rw_mgr_mem_calibrate_dq_dqs_centering()
with the correct flags set to trim down the code duplication.
Moreover, reorder the remnants in the function a little and
convert the function to return either 0 or -EIO in case of
success and failure respectively, to match the common return
value convention.
Signed-off-by: Marek Vasut <[email protected]>
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Brief clean, add kerneldoc.
Signed-off-by: Marek Vasut <[email protected]>
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Add kerneldoc.
Signed-off-by: Marek Vasut <[email protected]>
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Clean up coding style, mostly broken multiline formatting strings
in debug output. Also clean up data types and constify where applicable.
Signed-off-by: Marek Vasut <[email protected]>
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Move code around to get rid of the forward declaration. No change
to the actual code.
Signed-off-by: Marek Vasut <[email protected]>
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Add kerneldoc.
Signed-off-by: Marek Vasut <[email protected]>
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