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This reverts commit 431be621c6cbc72efd1d45fa36686a682cbb470a.
Section 3.3 of Reduced Gigabit Media Independent Interface (RGMII)
Version 2.0 (4/1/2002) details that a PHYs using a ~2ns internal delay
are referred to as RGMII-ID. This internal delay is optional.
Page 147-148 of the Marvell Doc. No. MV-S107146-U0 Rev. F details
timings of the RX/TX delays. We see that with the TX/RX_CLK delay
enabled, our RX/TX_CTL signal is shifted w.r.t CLK to reflect the delay
added.
In 431be62 there is no timing difference between RGMII and RGMII-ID, and
so programmers wanting to explicitly set their PHY to RGMII will find
that delay added anyway. This could throw off timing if that internal
delay is undesired.
We should be handling all 4 possible RGMII cases of PHY_INTERFACE_MODE:
RGMII, RGMII_ID, RGMII_TXID, and RGMII_RXID. Reverting 431be62
implements this.
See also m88e1111_config_init_rgmii_delays in the equivalent driver in
Linux (drivers/net/phy/marvell.c), which does not set these delays in
RGMII mode.
68e6eca was tested out on an 88E1512 PHY in RGMII-ID mode. This
reversion has been tested by myself on an 88E1518 in RGMII-ID mode. This
patch affects boards using this driver in "rgmii" mode, as the internal
delay will no longer be enabled. Namely kikwood-nsa310s.
Signed-off-by: Rufus Segar <[email protected]>
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As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.
Reported-by: Jonas Karlman <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.
This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.
Reported-by: Jonas Karlman <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Remove <common.h> from this driver directory and when needed
add missing include files directly.
Signed-off-by: Tom Rini <[email protected]>
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Import marvell_phy.h from Linux 5.14.y as of commit
a5de4be0aaaa6 ("net: phy: marvell10g: fix differentiation of 88X3310 from 88X3340")
and use it in marvell PHY driver instead of current ad-hoc macros.
Two of the PHY IDs are unknown to Linux, 88E1149S and 88E1680, for
those two, only sync the length of the hexadecimal number to 8 digits.
No functional change.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
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Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.
Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"
Signed-off-by: Marek Vasut <[email protected]>
Acked-by: Michal Simek <[email protected]>
Tested-by: Michal Simek <[email protected]> #microblaze (MANUAL_RELOC)
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As DM_ETH is required for all network drivers, it's now safe to
remove the non-DM_ETH support code.
Signed-off-by: Tom Rini <[email protected]>
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This patch adds basic support for the Marvell 88E1240 PHY.
This will be used by the upcoming ethernet support addition for the
Marvell MIPS Octeon EBB7304 platform.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Ramon Fried <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Aaron Williams <[email protected]>
Cc: Chandrakala Chavva <[email protected]>
Reviewed-by: Marek Behún <[email protected]>
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This patch adds support for the "marvell,reg-init" DT property, which
is used to describe board specific Marvell PHY register configurations
in the board dts file. This DT property is supported in the Linux Kernel
since a longer time. Adding it to U-Boot now, enables the boards which
describe the register settings in their DT files here as well.
I've included calling this marvell_of_reg_init() to all foo_config()
functions in this patch as well. If CONFIG_DM_ETH is not set, there is
no ofnode, or no "marvell,reg-init" property, the PHY initialization is
unchanged.
The function marvell_of_reg_init() is a port of the Linux version.
Please note that I explicitly did not add error checking and handling
to the U-Boot version, as this is basically not done for phy_read/write
in this Marvell PHY code.
This will be used by the upcoming ethernet support on the MIPS
Octeon EBB 7304 board.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Ramon Fried <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Aaron Williams <[email protected]>
Cc: Chandrakala Chavva <[email protected]>
Cc: Marek Behún <[email protected]>
Reviewed-by: Marek Behún <[email protected]>
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Move this uncommon header out of the common header.
Signed-off-by: Simon Glass <[email protected]>
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Move this uncommon header out of the common header.
Signed-off-by: Simon Glass <[email protected]>
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The PHY models of the Marvell 88E151x series are not reliably
distinguishable by their uid / PHY identifiers.
The 88E1510, 88E1512, 88E1514 and 88E1518 all have the same OUI and
model number and bits 3:0 in the PHY Identifier 2 (Page 0, Reg 3) are
described as HW revision number, but both 88E1510 and 88E1518 PHYs were
observed with the same HW rev number (1).
Before commit 83cfbeb0df9f ("net: phy: Fix mask so that we can identify
Marvell 88E1518"), the 88E151x were detected because the HW revision
bits were masked from the uid. After that change, 88E1510/12/18 were all
detected as 88E1518 and the 88E1510 specific code was no longer run.
I modified the mask to again ignore all four HW revision bits, removed
the 88E1510 specific code (board-specific LED/INTn setup), which was not
called since late 2016 anyway and renamed the config function and
phy_driver struct to the better fitting 88e151x.
The uid and mask bits 3:0 are now again the same as in the Linux kernel.
Signed-off-by: Clemens Gruber <[email protected]>
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We want to be able to include some other system headers in phy.h but
that requires us to have included common.h in the top-level first.
Also, common.h includes config.h as the first thing it does, so don't
include it directly.
Series-to: u-boot
Series-cc: Grygorii Strashko <[email protected]>
Seried-cc: ti
Series-process-log: sort, uniq
Cover-letter:
Prepare for net: phy: prevent uclass_eth device "node" field overwriting
Prepare for [1] so that it doesn't break the build for a bunch of
boards. There are a number of reasons this series broke the build
but none of them depend on changes in the series, so fix up those
situations ahead of applying that series.
[1] https://patchwork.ozlabs.org/cover/940104/
END
Signed-off-by: Joe Hershberger <[email protected]>
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When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.
In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.
This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.
Signed-off-by: Tom Rini <[email protected]>
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Commit 68e6ecadc551 ("net: phy: marvell 88e151x: Fix handling of RGMII
interface types") fixed the initialization of 88e151x phys, but made it
so that interfaces of type PHY_INTERFACE_MODE_RGMII had both RX and TX
delay bits cleared. The default (like in m88e1111s_config) is to have
both bits set.
Hence, this patch changes the behavior in the PHY_INTERFACE_MODE_RGMII
case so that both bits are set.
Signed-off-by: Mario Six <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Fix some style violations (mostly wrong indentions) in the Marvell PHY
driver.
Acked-by: Joe Hershberger <[email protected]>
Signed-off-by: Mario Six <[email protected]>
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This commit allows extended Marvell registers to be read with:
foo > mdio rx FEC 3.10
Reading from bus FEC
PHY at address 0:
3.16 - 0x1063
foo > mdio wx FEC 3.10 0x1011
The above code changes the way ETH connector LEDs blink.
Signed-off-by: Lukasz Majewski <[email protected]>
Reviewed-by: York Sun <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Commit a058052c changed the generic phy_reset() to clear all bits in
BMCR. This inevitably clears the ANEG bit. m88e1145 requires any
change to ANEG bit to be followed by a software reset. This seems to
be different from other PHYs. Implement read-modify-write procedure
for this PHY init.
Signed-off-by: York Sun <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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The 88E1518 code is programming the wrong registers for rgmii-id,
rgmii-txid and rgmii-rxid interfaces.
Since the PHY defaults to rgmii-id, it would appear that the code
was previously only used with sgmii and rgmii-id interfaces.
Tested on 88E1512 PHY in rgmii-id mode which is from the same family
as 88E1518.
Signed-off-by: Phil Edworthy <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Use some constants for the phy configuration instead of so many magic
numbers.
Signed-off-by: Joe Hershberger <[email protected]>
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Signed-off-by: Phil Edworthy <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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This device also works with the 88E1518 code, so we just adjust
the UID mask accordingly.
Signed-off-by: Phil Edworthy <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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The mask for the 88E1510 meant that the 88E1518 code would never be
used.
Signed-off-by: Phil Edworthy <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Add support for Marvell 88E1680 Integrated Octal
10/100/1000 Mbps Energy Efficient Ethernet Transceiver.
Signed-off-by: Dirk Eibach <[email protected]>
Signed-off-by: Mario Six <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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This corrects a build error on zynqmp.
Signed-off-by: Simon Glass <[email protected]>
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Commit a058052c "net: phy: do not read configuration register on reset",
changes the behaviour of the phy_reset function such that the state of
the BMCR register is not preserved during reset.
Change the config function for the m88e1310 so that it does not do a
reset after configuring auto-negotiation.
Signed-off-by: Nathan Rossi <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Michal Simek <[email protected]>
Cc: Stefan Roese <[email protected]>
Acked-by: Michal Simek <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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The patch
"net: phy: do not read configuration register on reset"
(sha1: a058052c358c3ecf5f394ff37def6a45eb26768c)
was causing regression on zynq zc702 board where Marwell 88e1118
phy was resetted after negotiation was setup.
Phy reset is done pretty early in phy_connect_dev() and doens't need to
be called again in phy code.
Signed-off-by: Michal Simek <[email protected]>
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Propagate error code from genphy_update_link() to phy startup().
Signed-off-by: Michal Simek <[email protected]>
Acked-by: Stephen Warren <[email protected]>
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Return -ETIMEDOUT if timeout happens.
Signed-off-by: Michal Simek <[email protected]>
Acked-by: Stephen Warren <[email protected]>
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With commit a058052c [net: phy: do not read configuration register on
reset], phy_reset() will clear the BMCR register. Resulting in bit 12
being cleared (A/N enable). This leads to autonegotiation link problems,
at least on the Marvell Armada ClearFog board. I suspect that other
boards using this driver will be affected as well.
At the of m88e1111s_config(), phy_reset() is called. This is not needed
for the PHY to load the changed configuration, as phy_reset() is called
a few lines before already. So lets call genphy_restart_aneg() here
instead to start the AN correctly.
Tested on clearfog.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Stefan Agner <[email protected]>
Cc: Hao Zhang <[email protected]>
Cc: Michal Simek <[email protected]>
Cc: Andy Fleming <[email protected]>
Cc: Joe Hershberger <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Instead of coding the soft PHY reset function multiple times in marvell.c,
lets call the common phy_reset() function from phy.c.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Stefan Agner <[email protected]>
Cc: Hao Zhang <[email protected]>
Cc: Michal Simek <[email protected]>
Cc: Andy Fleming <[email protected]>
Cc: Joe Hershberger <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Support the 88E1510 PHY which is very similar to the 88E1518.
I also set the INTn output and configured the LEDs.
Signed-off-by: Clemens Gruber <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Hao Zhang <[email protected]>
Cc: Michal Simek <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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- The EEE fixup magic should also be enabled for RGMII
- Improved comments
Signed-off-by: Clemens Gruber <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Hao Zhang <[email protected]>
Cc: Michal Simek <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512/88E1514
Rev A0, Errata Section 3.1 Marvell PHY has an errata which requires
that certain registers get written in order to restart
autonegotiation.
Signed-off-by: Hao Zhang <[email protected]>
Signed-off-by: Ivan Khoronzhuk <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Signed-off-by: Wolfgang Denk <[email protected]>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <[email protected]>
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This adds PHY initialization for Marvell Alaska 88E1310 PHY.
Signed-off-by: Sebastian Hesselbarth <[email protected]>
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This phy is used on zedboard (xilinx zynq platform).
Signed-off-by: Michal Simek <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Marvell 88E1118R has different uid then 88E1118.
Signed-off-by: Michal Simek <[email protected]>
CC: Andy Fleming <[email protected]>
CC: Zang Roy-R61911 <[email protected]>
CC: Kumar Gala <[email protected]>
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The original m88e1111s_config() does not do the SGMII mode
initialization and is buggy. Rewrite the function according to
3.0.6 kernel function m88e1111_config_init() in drivers/net/phy/marvell.c
Signed-off-by: Roy Zang <[email protected]>
Acked-by: Andy Fleming <[email protected]>
Cc: Kumar Gala <[email protected]>
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The tsec driver had a bunch of PHY drivers already written. This
converts them all into PHY Lib drivers, and serves as the first
set of PHY drivers for PHY Lib.
While doing that, cleaned up a number of magic numbers (though
not all of them, as PHY vendors like to keep their numbers as
magical as possible). Also, noticed that almost all of the
vitesse/cicada PHYs had the same config/parse/startup functions,
so those have been collapsed into one.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
Acked-by: Detlev Zundel <[email protected]>
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