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Add SPL_PHY_CADENCE_TORRENT configuration option to enable the Cadence
Torrent PHY driver in SPL stage. This is required for PCIe boot support
where SERDES configuration must be done early in the boot sequence
before loading the bootloader image over PCIe.
Signed-off-by: Hrushikesh Salunke <[email protected]>
Signed-off-by: Siddharth Vadapalli <[email protected]>
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cmn_refclk_<p/m> lines in Torrent SERDES are used for connecting an
external reference clock. cmn_refclk_<p/m> can also be configured to
output the reference clock. Model this derived reference clock as a
"clock" so that platforms like AM642 EVM can enable it.
This is used by PCIe to use the same refclk both in local SERDES
and remote device. Add support here to drive refclk out.
Based on: https://lore.kernel.org/all/[email protected]/
Signed-off-by: George McCollister <[email protected]>
Tested-by: Bryan Brattlof <[email protected]>
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In cdns_torrent_phy_probe the test for too many lanes configured does
not set an error code before taking the error path. This could lead to a
silent failure if the calling code does not detect the error. Add the
code to return -EINVAL in this case.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
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In cdns_sierra_pll_bind_of_clocks the variable 'i' is declared but never
assigned to before its value is used in a dev_err. Replace clk_names[i]
by the name passed to device_bind(), i.e., "pll_mux_clk". With that, the
clk_names[] array is unused and can therefore be removed.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
[jf: update description]
Signed-off-by: Jerome Forissier <[email protected]>
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This is a port of the corresponding commit in the Linux kernel which
adds the same support for the Cadence Torrent driver[0]. The commit
message below is taken as-is from the Linux kernel commit being ported.
The Torrent SERDES can support at most two different protocols (PHY types).
This only mandates that the device-tree sub-nodes used to represent the
configuration should describe links with at-most two different protocols.
The existing implementation however imposes an artificial constraint that
allows only two links (device-tree sub-nodes). As long as at-most two
protocols are chosen, using more than two links to describe them in an
alternating configuration is still a valid configuration of the Torrent
SERDES.
A 3-Link 2-Protocol configuration of the 4-Lane SERDES can be:
Lane 0 => Protocol 1 => Link 1
Lane 1 => Protocol 1 => Link 1
Lane 2 => Protocol 2 => Link 2
Lane 3 => Protocol 1 => Link 3
A 4-Link 2-Protocol configuration of the 4-Lane SERDES can be:
Lane 0 => Protocol 1 => Link 1
Lane 1 => Protocol 2 => Link 2
Lane 2 => Protocol 1 => Link 3
Lane 3 => Protocol 2 => Link 4
[0] https://github.com/torvalds/linux/commit/5b7b83a9839be643410c31d56f17c2d430245813
Signed-off-by: Hrushikesh Salunke <[email protected]>
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It is confusing to have both "$(PHASE_)" and "$(XPL_)" be used in our
Makefiles as part of the macros to determine when to do something in our
Makefiles based on what phase of the build we are in. For consistency,
bring this down to a single macro and use "$(PHASE_)" only.
Signed-off-by: Tom Rini <[email protected]>
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Simon Glass <[email protected]> says:
When the SPL build-phase was first created it was designed to solve a
particular problem (the need to init SDRAM so that U-Boot proper could
be loaded). It has since expanded to become an important part of U-Boot,
with three phases now present: TPL, VPL and SPL
Due to this history, the term 'SPL' is used to mean both a particular
phase (the one before U-Boot proper) and all the non-proper phases.
This has become confusing.
For a similar reason CONFIG_SPL_BUILD is set to 'y' for all 'SPL'
phases, not just SPL. So code which can only be compiled for actual SPL,
for example, must use something like this:
#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
In Makefiles we have similar issues. SPL_ has been used as a variable
which expands to either SPL_ or nothing, to chose between options like
CONFIG_BLK and CONFIG_SPL_BLK. When TPL appeared, a new SPL_TPL variable
was created which expanded to 'SPL_', 'TPL_' or nothing. Later it was
updated to support 'VPL_' as well.
This series starts a change in terminology and usage to resolve the
above issues:
- The word 'xPL' is used instead of 'SPL' to mean a non-proper build
- A new CONFIG_XPL_BUILD define indicates that the current build is an
'xPL' build
- The existing CONFIG_SPL_BUILD is changed to mean SPL; it is not now
defined for TPL and VPL phases
- The existing SPL_ Makefile variable is renamed to SPL_
- The existing SPL_TPL Makefile variable is renamed to PHASE_
It should be noted that xpl_phase() can generally be used instead of
the above CONFIGs without a code-space or run-time penalty.
This series does not attempt to convert all of U-Boot to use this new
terminology but it makes a start. In particular, renaming spl.h and
common/spl seems like a bridge too far at this point.
The series is fully bisectable. It has also been checked to ensure there
are no code-size changes on any commit.
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Use XPL_ as the symbol to indicate an SPL build. This means that SPL_ is
no-longer set.
Signed-off-by: Simon Glass <[email protected]>
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use dev_dbg() instead of dev_info() for debug related
prints.
Get's rid of below print from console.
"cdns,sierra serdes@5030000: sierra probed"
Signed-off-by: Roger Quadros <[email protected]>
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As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.
Reported-by: Jonas Karlman <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.
This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.
Reported-by: Jonas Karlman <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Remove <common.h> from this driver directory and when needed
add missing include files directly.
Signed-off-by: Tom Rini <[email protected]>
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Replace instances of http://www.ti.com with https://www.ti.com
Signed-off-by: Nishanth Menon <[email protected]>
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In commit 6f46c7441a9f ("phy: cadence: Sierra: Add a UCLASS_PHY device for
links"), a separate udevice of type UCLASS_PHY was created for each link.
Therefore, move the corresponding link operations under the link device.
Also, change the uclass of sierra phy to UCLASS_MISC as it is no longer the
phy device.
Fixes: 6f46c7441a9f ("phy: cadence: Sierra: Add a UCLASS_PHY device for links")
Signed-off-by: Aswath Govindraju <[email protected]>
Reviewed-by: Georgi Vlaev <[email protected]>
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In some cases, a single SerDes instance can be shared between two different
processors, each using a separate link. In these cases, the SerDes
configuration is done in an earlier boot stage. Therefore, add support to
skip reconfiguring, if it is was already configured beforehand.
Signed-off-by: Aswath Govindraju <[email protected]>
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Add register sequences for PCIe + QSGMII PHY multilink configuration.
Signed-off-by: Swapnil Jakhade <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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Add support for multilink configuration of Sierra PHY. Currently,
maximum two links are supported.
Signed-off-by: Swapnil Jakhade <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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Add single link PCIe register configurations for no SSC and internal
SSC. Also, add missing PMA lane registers for external SSC.
Signed-off-by: Swapnil Jakhade <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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PIPE phy status is used to communicate the completion of several PHY
functions. Check if PHY is ready for operation while configured for
PIPE mode during startup.
Signed-off-by: Swapnil Jakhade <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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Check if PMA cmn_ready is set indicating the startup process is complete.
Signed-off-by: Swapnil Jakhade <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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Add PHY PCS common register configuration sequences for single link.
Update single link PCIe register sequence accordingly.
Signed-off-by: Swapnil Jakhade <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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documentation
No functional change. Rename some regmap variables as mentioned in Sierra
register description documentation.
Signed-off-by: Swapnil Jakhade <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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Add support to get SSC type from DT.
Signed-off-by: Swapnil Jakhade <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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Sierra driver currently supports single link configurations only. Prepare
driver to support multilink multiprotocol configurations along with
different SSC modes.
Signed-off-by: Swapnil Jakhade <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has
two inputs, plllc_refclk (input from pll0_refclk) and refrcv (input from
pll1_refclk). Model PLL_CMNLC and PLL_CMNLC1 as a clock so that it's
possible to select one of these two inputs from device tree.
Signed-off-by: Aswath Govindraju <[email protected]>
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Add a driver of type UCLASS_PHY for each of the link nodes in the serdes
instance.
Signed-off-by: Aswath Govindraju <[email protected]>
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Add missing clk_disable_unprepare() in cdns_sierra_phy_remove().
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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Instead of having separate structure members for each input clock, add
an array for the input clocks within "struct cdns_sierra_phy". This is
in preparation for adding more input clocks required for supporting
additional clock combination.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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No functional change. Group devm_reset_control_get() and
devm_reset_control_get_optional() to a separate function.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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No functional change. Group all devm_clk_get_optional() to a
separate function.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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Cadence Sierra PHY driver registers PHY using devm_phy_create()
for all sub-nodes of Sierra device tree node. However Sierra device
tree node can have sub-nodes for the various clocks in addtion to the
PHY. Use devm_phy_create() only for nodes with name "phy" (or "link"
for old device tree) which represent the actual PHY.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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Commit 39b823381d9d ("phy: cadence: Add driver for Sierra PHY")
de-asserts PHY_RESET even before the configurations are loaded in
phy_init(). However PHY_RESET should be de-asserted only after
all the configurations has been initialized, instead of de-asserting
in probe. Fix it here.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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Updated values of USB3 related Sierra PHY registers.
This change fixes USB3 device disconnect issue observed
while enternig U1/U2 state.
Signed-off-by: Sanket Parmar <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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Search for "phy" in the subnode names, to syncup with kernel.
Signed-off-by: Aswath Govindraju <[email protected]>
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Add driver for Torrent SERDES.
Signed-off-by: Aswath Govindraju <[email protected]>
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Add a Sierra PHY driver with PCIe and USB support.
This driver is a port from the mainline linux driver.
The PHY has multiple lanes, which can be configured into
groups, and a generic PHY device is created for each group.
There are two resets controlling the overall PHY block, one
to enable the APB interface for programming registers, and
another to enable the PHY itself. Additionally there are
resets for each PHY lane.
The PHY can be configured in hardware to read register
settings from ROM, or they can be written by the driver.
The sequence of operation on startup is to enable the APB
bus, write the PHY registers (if required) for each lane
group, and then enable the PHY. Each group of lanes
can then be individually controlled using the power_on()/
power_off() function for that generic PHY
One difference with the linux driver is that the PHY is
always reset after it is powered-on. This is because role
switching is not supported in u-boot and the cable
orientation is handled by the PHY reset.
Signed-off-by: Jean-Jacques Hiblot <[email protected]>
Signed-off-by: Alan Douglas <[email protected]>
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Vignesh Raghavendra <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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