| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2026-03-16 | phy: ti: Add config to enable J721E WIZ SERDES wrapper at SPL stage | Hrushikesh Salunke | |
| Add SPL_PHY_J721E_WIZ configuration option to enable the WIZ SERDES wrapper driver in SPL stage. This is required for PCIe boot support where SERDES configuration must be done early in the boot sequence before loading the bootloader image over PCIe. Signed-off-by: Hrushikesh Salunke <[email protected]> Signed-off-by: Siddharth Vadapalli <[email protected]> | |||
| 2021-07-27 | phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC | Jean-Jacques Hiblot | |
| Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES wrapper used to configure some of the input signals to the SERDES. It is used with both Sierra(16G) and Torrent(10G) SERDES. This driver configures three clock selects (pll0, pll1, dig) and supports resets for each of the lanes. This is an adaptation of the linux driver. Signed-off-by: Jean-Jacques Hiblot <[email protected]> Signed-off-by: Vignesh Raghavendra <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lokesh Vutla <[email protected]> Link: https://lore.kernel.org/r/[email protected] | |||
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