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This patch cleans the vendor code of DDR initialization up, converts the
driver to fit in DM framework and use a firmware[1] packaged by binman to
ship PHY configuration.
Currently the driver is only capable of initializing the controller to
work with dual-rank 3733MHz LPDDR4, which is shipped by 16GiB variants
of LicheePi 4A boards and I could test with. Support for other
configurations could be easily added later.
Link: https://github.com/ziyao233/th1520-firmware # [1]
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Use PHASE_ as the symbol to select a particular XPL build. This means
that SPL_TPL_ is no-longer set.
Update the comment in bootstage to refer to this symbol, instead of
SPL_
Signed-off-by: Simon Glass <[email protected]>
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Use the new symbol to refer to any 'SPL' build, including TPL and VPL
Signed-off-by: Simon Glass <[email protected]>
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Add driver for AST2700 to initialize DRAM in SPL.
This patch also refactors the Kconfig dependency of
Aspeed DRAM drivers as some of them are shared among
the file structures of RV and ARM ISAs.
Signed-off-by: Chia-Wei Wang <[email protected]>
Acked-by: Leo Yu-Chi Liang <[email protected]>
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Rename ARCH_RMOBILE to ARCH_RENESAS because all the chips are made
by Renesas, while only a subset of them is from the R-Mobile
line.
Use the following command to perform the rename:
"
$ git grep -l 'ARCH_RMOBILE' | xargs -I {} sed -i 's@ARCH_RMOBILE@ARCH_RENESAS@g' {}
"
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Paul Barker <[email protected]>
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The Allwinner R528/T113-s/D1/D1s SoCs all share the same die, so use the
same DRAM initialisation code.
Make use of prior art here and lift some code from awboot[1], which
carried init code based on earlier decompilation efforts, but with a
GPL2 license tag.
This code has been heavily reworked and cleaned up, to match previous
DRAM routines for other SoCs, and also to be closer to U-Boot's coding
style and support routines.
The actual DRAM chip timing parameters are included in the main file,
since they cover all DRAM types, and are protected by a new Kconfig
CONFIG_SUNXI_DRAM_TYPE symbol, which allows the compiler to pick only
the relevant settings, at build time.
The relevant DRAM chips/board specific configuration parameters are
delivered via Kconfig, so this code here should work for all supported
SoCs and DRAM chips combinations.
Signed-off-by: Andre Przywara <[email protected]>
Tested-by: Sam Edwards <[email protected]>
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Add support for Schneider Electric RZ/N1D and RZ/N1S boards, which
are based on the Reneasas RZ/N1 SoC devices.
The intention is to support both boards using a single defconfig, and to
handle the differences at runtime.
Signed-off-by: Ralph Siemsen <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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Driver for Cadence EDAC DDR controller, as found in the Renesas RZ/N1.
Signed-off-by: Ralph Siemsen <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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Add driver for StarFive JH7110 to support ddr initialization in SPL.
Signed-off-by: Yanhong Wang <[email protected]>
Tested-by: Conor Dooley <[email protected]>
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ram-uclass is building irrespective of whether TPL_DM
or SPL_DM is enabled. So control the ram uclass build
based on TPL/SPL_DM.
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Create a new CONFIG_K3_DDRSS option to select the common parts of the
k3-ddrss driver. Also introduce a choice that depends on the top level
option to select CONFIG_K3_J721E_DDRSS for j721e support, and update
corresponding Kconfig as required.
Signed-off-by: Dave Gerlach <[email protected]>
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Rename the k3-j721e folder under drivers/ram to k3-ddrss in preparation
of introducing additional support for other platforms to the same
driver.
Signed-off-by: Dave Gerlach <[email protected]>
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to improve the maintainability. It is more easier to modify and add
configurations of the driver in the centralized ram driver directory.
Signed-off-by: Dylan Hung <[email protected]>
Reviewed-by: Ryan Chen <[email protected]>
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This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot
repository. It currently supports DDR4 on Octeon 3. It can be later
extended to support also DDR3 and Octeon 2 platforms.
Part 3 includes the DIMM SPD handling code and the Kconfig / Makefile
integration.
Signed-off-by: Aaron Williams <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Add driver for fu540 to support ddr initialization in SPL.
This driver is based on FSBL
(https://github.com/sifive/freedom-u540-c000-bootloader.git)
Signed-off-by: Pragnesh Patel <[email protected]>
Tested-by: Bin Meng <[email protected]>
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Add SDRAM driver for i.MXRT SoCs.
Signed-off-by: Giulio Benetti <[email protected]>
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The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper
logic to integrate these blocks in the device. The DDR subsystem is
used to provide an interface to external SDRAM devices which can be
utilized for storing program or data. Introduce support for the
DDR controller and DDR phy within the DDR subsystem.
Signed-off-by: Kevin Scholz <[email protected]
Signed-off-by: Lokesh Vutla <[email protected]>
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This patch adds a DDR3 driver for MT7629 SoC.
Signed-off-by: Wu Zou <[email protected]>
Signed-off-by: Ryder Lee <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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K3 based AM654 devices has DDR memory subsystem that comprises
Synopys DDR controller, Synopsis DDR phy and wrapper logic to
intergrate these blocks into the device. This DDR subsystem
provides an interface to external SDRAM devices. Adding support
for the initialization of the external SDRAM devices by
configuring the DDRSS registers and using the buitin PHY
routines.
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
Signed-off-by: Andreas Dannenberg <[email protected]>
Signed-off-by: Keerthy <[email protected]>
Signed-off-by: Schuyler Patton <[email protected]>
Signed-off-by: James Doublesin <[email protected]>
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Complete in the drivers directory the work started with
commit 83d290c56fab ("SPDX: Convert all of our single
license tags to Linux Kernel style").
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Patrick Delaunay <[email protected]>
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Add a RAM driver for the MPC83xx architecture.
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Mario Six <[email protected]>
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Add driver and binding for stm32mp1 ddr controller and phy
Signed-off-by: Patrick Delaunay <[email protected]>
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This adds a DRAM controller driver for the RK3368 and places it in
drivers/ram/rockchip (where the other DM-enabled DRAM controller
drivers for rockchip devices should also be moved eventually).
At this stage, only the following feature-set is supported:
- DDR3
- 32-bit configuration (i.e. fully populated)
- dual-rank (i.e. no auto-detection of ranks)
- DDR3-1600K speed-bin
This driver expects to run from a TPL stage that will later return to
the RK3368 BROM. It communicates with later stages through the
os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR
init code).
Unlike other DMC drivers for RK32xx and RK33xx parts, the required
timings are calculated within the driver based on a target frequency
and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this
time).
The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0)
register for controlling the operation of its (single-channel) DRAM
controller in the GRF block. This provides for selecting DDR3, mobile
DDR modes, and control low-power operation.
As part of this change, DDRC0_CON0 is also added to the GRF structure
definition (at offset 0x600).
Signed-off-by: Philipp Tomsich <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Signed-off-by: Vikas Manocha <[email protected]>
cc: Christophe KERELLO <[email protected]>
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Add a test to confirm that we can probe this device and get information on
the available RAM.
Signed-off-by: Simon Glass <[email protected]>
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Add support for a driver which sets up DRAM and can return information about
the amount of RAM available. This is a first step towards moving RAM init
to driver model.
Signed-off-by: Simon Glass <[email protected]>
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