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Since this set of drivers suports four Tegra SoC generations, lets name it
just 'tegra'.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Reviewed-by: Peter Robinson <[email protected]>
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Existing Tegra30 DSI configuration is fully compatible with Tegra20.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Use DSI message flag to set correct speed mode for message transfer.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Switch from PANEL_UCLASS to VIDEO_BRIDGE_UCLASS since now
Tegra DC driver has bridge support.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Establish the backlight as a DC display controller child.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Implement child binding helper within DC bind to support DC PWM backlight
feature.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Video operations are not required by the Tegra Display Controller
and should therefore be removed.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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If device uses native Tegra DSI or HDMI, DC clock MUST use the same
parent as DSI/HDMI clock uses. Hence remove need in device tree
configuration and satisfy this condition by default.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Use OF graph as a main bridge/panel source, preserving
backwards compatibility with phandle implementation.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Rework existing DC driver configuration to support bridges (both external
and internal DSI and HDMI controllers) and align video devices chain logic
with Linux implementation. Additionally, this should improve communication
between DC and internal DSI/HDMI controllers.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Tegra platforms feature native HDMI support. Implement a driver to enable
functionality. This driver will initially support Tegra 2 and 3, with
future extensibility.
Co-developed-by: Jonas Schwöbel <[email protected]>
Signed-off-by: Jonas Schwöbel <[email protected]>
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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reset setup
Introduce a simplified HOST1X driver, limited to the basic clock and reset
initialization of the bus.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Re-design MIPI calibration driver to fit T124.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Tegra K1 is fully compatible with existing DC and DSI implementation
using Tegra 4 data.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Parametrize DSI configuration by passing DC source pipe. This
should resolve possible failure if second DC is used with DSI
for some reason.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Use Linux DSI driver approach to calculate lanes for ganged mode.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Calculate packet parameters for video mode same way it is done or
command mode, by halving timings plugged into equations.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Move SOL delay calculation outside of video mode conditions.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Align U-Boot DSI ganged mode implementation with the Linux kernel's
implementation.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Switch to struct clk instead of working with plain clock id.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Switch to Linux-like approach of DSI panel binding as a DSI
controllers child node.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Mainly unification and improving of readability.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Since pinmux driver now is available for Tegra 2, these parts may
be removed from here and defined either in device tree or in
the device board files.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Switch to struct clk instead of working with plain clock id.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Implement ganged mode support for the Tegra DSI driver. The DSI host
controller to gang up with is specified via a phandle in the device tree
and the resolved DSI host controller used for the programming of the
ganged-mode registers.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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It seems that DECLARE_GLOBAL_DATA_PTR use is not needed and video system
works perfectly fine without it.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Use existing nvidia,head device tree property to get DC controller id.
Acked-by: Thierry Reding <[email protected]>
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.
Reported-by: Jonas Karlman <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.
This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.
Reported-by: Jonas Karlman <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Remove <common.h> from this driver directory and when needed
add missing include files directly.
Reviewed-by: Peter Robinson <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Shift the backlight set further to prevent visual glitches on
panel init.
Signed-off-by: Jonas Schwöbel <[email protected]>
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
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According to Thierry Reding's commit in the linux kernel
976cebc35bed0456a42bf96073a26f251d23b264
"drm/tegra: dsi: Make FIFO depths host parameters"
correct depth of the video FIFO is 1920 *words* no *bytes*
Tested-by: Ion Agorria <[email protected]> # HTC One X
Tested-by: Svyatoslav Ryhel <[email protected]> # Nvidia Tegratab T114
Signed-off-by: Jonas Schwöbel <[email protected]>
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
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Configuration for DC driver command mode is not required for
every panel. Removed.
Tested-by: Ion Agorria <[email protected]> # HTC One X
Tested-by: Svyatoslav Ryhel <[email protected]> # Nvidia Tegratab T114
Signed-off-by: Jonas Schwöbel <[email protected]>
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
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Implement reset use to discard any changes which could have been
applied to DSI before and can interfere with current configuration.
Tested-by: Ion Agorria <[email protected]> # HTC One X
Tested-by: Svyatoslav Ryhel <[email protected]> # Nvidia Tegratab T114
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Existing Tegra DSI driver mostly fits T114 apart MIPI calibration
which on T114 has dedicated driver. To resolve this MIPI calibration
logic was split for pre-T114 and T114+ devices.
Tested-by: Ion Agorria <[email protected]> # HTC One X
Tested-by: Svyatoslav Ryhel <[email protected]> # Nvidia Tegratab T114
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
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Dedicated MIPI calibration driver is used on T114 and newer. Before
T114 MIPI calibration registers were part of VI and CSI.
Tested-by: Svyatoslav Ryhel <[email protected]> # Nvidia Tegratab T114
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
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Based on Thierry Reding's Linux commit:
'commit 1716b1891e1de05e2c20ccafa9f58550f3539717
("drm/tegra: rgb: Parameterize V- and H-sync polarities")'
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
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Fill the framebuffer memory with zeros to avoid visual glitches.
Signed-off-by: Jonas Schwöbel <[email protected]>
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
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The goal of panel_set_backlight() is to enable backlight. Hence,
it should be called at the probe end.
Signed-off-by: Jonas Schwöbel <[email protected]>
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
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Framebuffer address should not be a pointer.
Signed-off-by: Jonas Schwöbel <[email protected]>
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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If DISP1 is a PLLD/D2 child, it cannot go over 370MHz. The cause
of this is not quite clear. This can be overcomed by further
halving the PLLD/D2 if the target parent rate is over 800MHz.
This way DISP1 and DSI clocks will have the same frequency. The
shift divider in this case has to be calculated from the
original PLLD/D2 frequency and is passed from the DSI driver.
Tested-by: Andreas Westman Dorcsak <[email protected]> # ASUS Grouper E1565
Tested-by: Ion Agorria <[email protected]> # HTC One X
Tested-by: Svyatoslav Ryhel <[email protected]> # Nvidia Tegratab T114
Tested-by: Jonas Schwöbel <[email protected]> # Microsoft Surface 2
Signed-off-by: Jonas Schwöbel <[email protected]>
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Acked-by: Thierry Reding <[email protected]>
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Add powergate use on T114 to complete resetting of DC.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
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T30+ SOC have second PLLD - PLLD2 which can be actively used by
DC and act as main DISP1/2 clock parent.
Tested-by: Agneli <[email protected]> # Toshiba AC100 T20
Tested-by: Robert Eckelmann <[email protected]> # ASUS TF101
Tested-by: Andreas Westman Dorcsak <[email protected]> # ASUS Grouper E1565
Tested-by: Ion Agorria <[email protected]> # HTC One X
Tested-by: Svyatoslav Ryhel <[email protected]> # Nvidia Tegratab T114
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
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Tegra SoC has 2 independent display controllers called DC_A and
DC_B, they are handled differently by internal video devices like
DSI and HDMI controllers so it is important for last to know
which display controller is used to properly set up registers.
To achieve this, a pipe field was added to pdata to pass display
controller id to internal Tegra SoC devices.
Tested-by: Agneli <[email protected]> # Toshiba AC100 T20
Tested-by: Robert Eckelmann <[email protected]> # ASUS TF101
Tested-by: Andreas Westman Dorcsak <[email protected]> # ASUS Grouper E1565
Tested-by: Ion Agorria <[email protected]> # HTC One X
Tested-by: Svyatoslav Ryhel <[email protected]> # Nvidia Tegratab T114
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Consolidate HD headers and place the result into video/tegra20
since it is used only by devices from this directory.
Tested-by: Agneli <[email protected]> # Toshiba AC100 T20
Tested-by: Robert Eckelmann <[email protected]> # ASUS TF101
Tested-by: Andreas Westman Dorcsak <[email protected]> # ASUS Grouper E1565
Tested-by: Ion Agorria <[email protected]> # HTC One X
Tested-by: Svyatoslav Ryhel <[email protected]> # Nvidia Tegratab T114
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
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Subtracting 1 from x and y fixes image shifting on rotated
panels.
Tested-by: Robert Eckelmann <[email protected]> # ASUS Grouper E1565
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
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Diverge DC driver setup to better fit each of supported generations
of Tegra SOC.
Tested-by: Agneli <[email protected]> # Toshiba AC100 T20
Tested-by: Robert Eckelmann <[email protected]> # ASUS TF101
Tested-by: Andreas Westman Dorcsak <[email protected]> # ASUS Grouper E1565
Tested-by: Ion Agorria <[email protected]> # HTC One X
Tested-by: Svyatoslav Ryhel <[email protected]> # Nvidia Tegratab T114
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Now that we have time conversion defines from in time.h there is no need
for each driver to define their own version.
Signed-off-by: Igor Prusov <[email protected]>
Reviewed-by: Svyatoslav Ryhel <[email protected]> # tegra
Reviewed-by: Eugen Hristev <[email protected]> #at91
Reviewed-by: Caleb Connolly <[email protected]> #qcom geni
Reviewed-by: Stefan Bosch <[email protected]> #nanopi2
Reviewed-by: Patrice Chotard <[email protected]>
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With the commit 4fcba5d556b4 ("regulator: implement basic reference
counter") the return value of regulator_set_enable may be EALREADY or
EBUSY for fixed/gpio regulators and may be further expanded on all
regulators.
Change to use the more relaxed regulator_set_enable_if_allowed to
continue if regulator already was enabled or disabled.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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