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path: root/drivers/video/zynqmp
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2026-02-17treewide: Clean up DECLARE_GLOBAL_DATA_PTR usagePeng Fan
Remove DECLARE_GLOBAL_DATA_PTR from files where gd is not used, and drop the unnecessary inclusion of asm/global_data.h. Headers should be included directly by the files that need them, rather than indirectly via global_data.h. Reviewed-by: Patrice Chotard <[email protected]> #STMicroelectronics boards and STM32MP1 ram test driver Tested-by: Anshul Dalal <[email protected]> #TI boards Acked-by: Yao Zi <[email protected]> #TH1520 Signed-off-by: Peng Fan <[email protected]>
2025-10-09video: zynqmp: Prevent use of uninitialised variablesAndrew Goodbody
The variables 'offset_matrix' and 'csc_matrix' will be used uninitialised if video->is_rgb is false. Correct the logic so the attempt to use uninitialised variables is not made. Also remove the use of these variables as they seem to serve no useful purpose just being aliases for arrays. This issue was found by Smatch. Signed-off-by: Andrew Goodbody <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2025-06-14drivers: use lowercase hex prefix styleE Shattow
Use consistent lowercase hex prefix style in drivers/* Does not change hex prefix case in allcaps uppercase style error messages Signed-off-by: E Shattow <[email protected]>
2024-12-11video: zynqmp: Add support for resetMichal Simek
In Kria SOM configuration DP is under reset and access to DP is causing hang that's why call reset at probe to avoid this situation. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/0504474a91a9839828aecd37f8855fd154cdf2e1.1733742708.git.michal.simek@amd.com
2024-08-26zynqmp: Avoid setting the framebuffer addressSimon Glass
This is handled by driver model so this driver should not be setting the framebuffer address. Drop the assignment. Signed-off-by: Simon Glass <[email protected]>
2024-05-20Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"Tom Rini
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <[email protected]> Signed-off-by: Tom Rini <[email protected]>
2024-05-19Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""Tom Rini
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <[email protected]> Signed-off-by: Tom Rini <[email protected]>
2024-05-07video: Remove <common.h> and add needed includesTom Rini
Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <[email protected]> Signed-off-by: Tom Rini <[email protected]>
2023-06-12video: zynqmp: Enable 1024x768 resolutionMichal Simek
Add support for 1024x768 60p resolution and set it up this resolution by default. This resolution is still able to use only one GT line. But for example 800x600 60p has some issues with settings. That's why extend this table by tested resolutions. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/957e1e85a05744326ec2606dadc1af6e69976f37.1684312924.git.michal.simek@amd.com
2023-06-12video: zynqmp: Driver for Xilinx ZynqMP DisplayPort SubsystemVenkatesh Yadav Abbarapu
The Xilinx ZynqMP SoC has a hardened display pipeline named DisplayPort Subsystem. It includes a buffer manager, blender, an audio mixer and a DisplayPort source controller (transmitter). The DisplayPort controller can source data from memory (non-live input) or the stream (live input). The DisplayPort controller is responsible for managing the link and physical layer functionality. The controller packs audio/video data into transfer units and sends them over the main link. The link rate and lane counts can be selected based on the application bandwidth requirements. The DisplayPort pipeline consists of the DisplayPort direct memory access (DMA) for fetching data from memory. The DisplayPort DMA controller (DPDMA) supports up to six input channels as non-live input. This driver supports the DisplayPort Subsystem and implements 1)640x480 resolution 2)RGBA8888 32bpp format 3)DPDMA channel 3 for Graphics 4)Non-live input 5)Fixed 5.4G link rate 6)Tested on ZCU102 board There will be additional work to configure GT lines based on DT, higher resolutions, support for more compressed video formats, spliting code to more files, add support for EDID, audio support, using clock framework for all clocks and in general code clean up. Codevelop-by: Michal Simek <[email protected]> Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/5c1567b63d0280dacc7efba2998857c399c25358.1684312924.git.michal.simek@amd.com
2023-06-12video: move zynqmp files to subdirectoryVenkatesh Yadav Abbarapu
Place zynqmp files and headers in custom driver subdirectory. Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/9aae6d217f0673c310818e3de38bb239c79c060c.1684312924.git.michal.simek@amd.com