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On the i.MX8M Mini, ret = clk_set_rate() sets ret to the value of the
rate the clock was able to set. When checking for errors, it only
checks that it is not NULL. Since positive numbers are not errors,
only check for negative numbers when handling errors.
Fixes: 383fded70c4f ("spi: nxp_fspi: new driver for the FlexSPI controller")
Signed-off-by: Adam Ford <[email protected]>
Reviewed-by: Pratyush Yadav <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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The code was processed with unifdef utility to omit portions not
relevant to A38x and DDR3. This removes usage of many macros, including
A70X0, A80X0 and A3900. It seems that the unifdef utility did not remove
the macros from #else comment.
Signed-off-by: Marek Behún <[email protected]>
Tested-by: Chris Packham <[email protected]>
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Bump version of a38x DDR3 trianing to version 14.0.0 to reflect the
version in the mv-ddr-devel branch of upstream repository
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.
There is a new version numbering system, where after 18.12.0 came
1.0.0, 2.0.0, and so on until 14.0.0. So 14.0.0 is newer than 18.12.0.
Signed-off-by: Marek Behún <[email protected]>
Tested-by: Chris Packham <[email protected]>
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commit 56db5d1464b44df10a02b99e615ebd6f6a35c428 upstream.
@pali suggested this change
In commit 6285efb ("mv_ddr: add support for twin-die combined memory
device") was added support for twin-die combined memory device and
default value for explicitly uninitialized structure members is zero, s
also twin_die_combined is initialized to zero. Which means COMBINED
value.
As prior this commit there was no support for twin-die combined memory
device, default value for twin_die_combined should be NOT_COMBINED. This
change change order of enum mv_ddr_twin_die to ensure that NOT_COMBINED
has value zero.
Signed-off-by: heaterC <[email protected]>
Signed-off-by: Marek Behún <[email protected]>
Tested-by: Chris Packham <[email protected]>
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commit 2bdd12dd68b1f8e27a03a3443ae49a09a14c18e4 upstream.
The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes code in ddr3_training.c.
Import this change to remain consistent with upstream.
Signed-off-by: Marek Behún <[email protected]>
Tested-by: Chris Packham <[email protected]>
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commit c8b301463d508c807a33f7b7eaea98bbda4aa35e upstream.
The funtion returnd cs size in byte instead of MB, that cause
calculation error since the caller was expected to get u32 and when he
got above 4G it refers it as 0.
The fix was to get the cs memory size from function as in MB and then
multiply it by 1MB.
Signed-off-by: Moti Buskila <[email protected]>
Reviewed-by: Kostya Porotchkin <[email protected]>
Signed-off-by: Marek Behún <[email protected]>
Tested-by: Chris Packham <[email protected]>
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commit d653b305d0b3da9727c49124683f1a6d95d5c9a5 upstream.
The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header ddr_topology_def.h.
Import this header change to remain consistent with upstream.
Signed-off-by: Marek Behún <[email protected]>
Tested-by: Chris Packham <[email protected]>
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commit 20c89a28548cdab11f88d2ec8936344af0686a1e upstream.
WL phase correcion stage is failing while using bus_width of 16bit, not
to be fix this stage is un-necessary when working with bus_width of 16
bit.
Signed-off-by: Moti Buskila <[email protected]>
Reviewed-by: Kostya Porotchkin <[email protected]>
Signed-off-by: Marek Behún <[email protected]>
Tested-by: Chris Packham <[email protected]>
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commit 6285efb8a118940877522c4c07bd7c64569b4f5f upstream.
the twin-die combined memory device should be treatened as X8
device and not as X16 one
Signed-off-by: Moti Buskila <[email protected]>
Reviewed-by: Kostya Porotchkin <[email protected]>
[ - the default value for twin_die_combined is set to NOT_COMBINED for
all boards, as this was default behaviour prior this change ]
Signed-off-by: Marek Behún <[email protected]>
Tested-by: Chris Packham <[email protected]>
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commit 994509eb4fe6771d92cd06314c37895098ac48fa upstream.
Signed-off-by: Moti Buskila <[email protected]>
Reviewed-by: Kostya Porotchkin <[email protected]>
Signed-off-by: Marek Behún <[email protected]>
Tested-by: Chris Packham <[email protected]>
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commit 2d3b9437cf38c06c4330e0de07f29476197f5e04 upstream.
The ODT enable heuristic based on active chip-selects is not always
correct. Some board might use two chip-selects, but have only one ODT
line connected. Allow board specific mv_ddr_topology_map to directly set
the ODT configuration register value.
Signed-off-by: Baruch Siach <[email protected]>
Reviewed-by: Moti Buskila <[email protected]>
Reviewed-by: Nadav Haklai <[email protected]>
Reviewed-by: Kostya Porotchkin <[email protected]>
Signed-off-by: Marek Behún <[email protected]>
Tested-by: Chris Packham <[email protected]>
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commit 3908e20c6c520339e9bddb566823ae5e065d5218 upstream.
The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header ddr_topology_def.h.
Import this header change to remain consistent with upstream.
Signed-off-by: Marek Behún <[email protected]>
Tested-by: Chris Packham <[email protected]>
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commit ab9240402a70cc02496683971779e75eff410ab4 upstream.
- function mv_ddr_spd_die_capacity_user_get() has a bug,
since it insert a user memory enum to it,
instead of SPD memory enum (which are different)
- fix: remove mv_ddr_spd_die_capacity_user_get() function.
- memory size with 64 and 32 bit already calculated correctly
at mv_ddr_mem_sz_per_cs_get() function
Signed-off-by: Moti Buskila <[email protected]>
Reviewed-by: Stefan Chulski <[email protected]>
Reviewed-by: Alex Leibovich <[email protected]>
Reviewed-by: Kostya Porotchkin <[email protected]>
Signed-off-by: Marek Behún <[email protected]>
Tested-by: Chris Packham <[email protected]>
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commit 0b5adedd4ced9b8f528faad1957d4d69e95759ef upstream.
Signed-off-by: Moti Buskila <[email protected]>
Reviewed-by: Alex Leibovich <[email protected]>
Reviewed-by: Kostya Porotchkin <[email protected]>
Signed-off-by: Marek Behún <[email protected]>
Tested-by: Chris Packham <[email protected]>
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commit 6c705ebc0d70f67ed7cae83ad1978c3305ef25be upstream.
The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header mv_ddr_topology.h.
Import this header change to remain consistent with upstream.
Signed-off-by: Marek Behún <[email protected]>
Tested-by: Chris Packham <[email protected]>
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commit 61a8910998d7b553e80f600ebe8147a8b98f0945 upstream.
Required changes made for 32bit ddr support.
An update is made to the topology map, according to
bus_act_mask, set in the dram_port.c
Signed-off-by: Alex Leibovich <[email protected]>
Reviewed-by: Kostya Porotchkin <[email protected]>
Signed-off-by: Marek Behún <[email protected]>
Tested-by: Chris Packham <[email protected]>
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commit 32800667b375ebd1f82120da0f3479b1cf52d96d upstream.
Required changes made for 32bit ddr support.
An update is made to the topology map, according to
bus_act_mask, set in the dram_port.c
Signed-off-by: Alex Leibovich <[email protected]>
Reviewed-by: Nadav Haklai <[email protected]>
Reviewed-by: Kostya Porotchkin <[email protected]>
Signed-off-by: Marek Behún <[email protected]>
Tested-by: Chris Packham <[email protected]>
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commit a165037ec26f301be75e1fabc263643683e85255 upstream.
The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header ddr_topology_def.h.
Import this header change to remain consistent with upstream.
Signed-off-by: Marek Behún <[email protected]>
Tested-by: Chris Packham <[email protected]>
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commit ce62bef8fac559e27245259882e45f19cdc293ad upstream.
- fix JIRA A7K8K-5056
- remove TEST_PATTERN write at the load patern stage earlier to WL SUP stage
- the WL SUP stage already writes this pattern to the memory, if the pattern exist at the memory
then the algorithm will fail, since it think that there are no phase to correct
Signed-off-by: Moti Buskila <[email protected]>
Reviewed-by: Kostya Porotchkin <[email protected]>
Signed-off-by: Marek Behún <[email protected]>
Tested-by: Chris Packham <[email protected]>
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Linux displays the real PCIe card connected to a mvebu PCIe slot as
device 0, not 1. This is done by setting local dev number to 1, so that
the local "Marvell Memory controller" device is on address 1.
Let's do it also in U-Boot.
With this commit the pci command in U-Boot prints something like:
=> pci
Scanning PCI devices on bus 0
BusDevFun VendorId DeviceId Device Class Sub-Class
_____________________________________________________________
00.00.00 0x168c 0x003c Network controller 0x80
Signed-off-by: Marek Behún <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Phil Sutter <[email protected]>
Cc: Mario Six <[email protected]>
Cc: Baruch Siach <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Refactor validation of bdf parameter in mvebu_pcie_read/write_config
functions.
We can simplify the code by putting the validation into separate
function.
Also there are always only two devices visible on local bus:
* on slot configured by function mvebu_pcie_set_local_dev_nr()
(by default this register is set to 0) there is a
"Marvell Memory controller", which isn't useful in root complex
mode,
* on all other slots the real PCIe card connected to the PCIe slot.
We can simplify the code even more by simply allowing access only to
the real PCIe card.
Signed-off-by: Marek Behún <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Phil Sutter <[email protected]>
Cc: Mario Six <[email protected]>
Cc: Baruch Siach <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Other drivers (aardvark, intel_fpga) print "(addr,size,val)" when
debugging is enabled. Print size for pci_mvebu as well.
Signed-off-by: Marek Behún <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Phil Sutter <[email protected]>
Cc: Mario Six <[email protected]>
Cc: Baruch Siach <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Write bdf address in a same way in mvebu_pcie_read/write_config.
Signed-off-by: Marek Behún <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Phil Sutter <[email protected]>
Cc: Mario Six <[email protected]>
Cc: Baruch Siach <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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PCI uclass maps PCI bus numbers to the seq member of struct udevice.
Use dev_seq(dev) as the bus number in mvebu_pcie_probe instead of an
incrementing a static variable.
Signed-off-by: Marek Behún <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Phil Sutter <[email protected]>
Cc: Mario Six <[email protected]>
Cc: Baruch Siach <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Fix usage of VL805 XHCI PCIe controller when it is connected via PCIe to
Armada 3720 SOC. Without this U-Boot crashes when trying to access
enumerated USB devices connected to this XHCI PCIe controller.
This should be done according to the PCIe Link Initialization sequence, as
defined in Marvell Armada 3720 Functional Specification.
Linux has this code too.
Signed-off-by: Pali Rohár <[email protected]>
Reviewed-by: Marek Behún <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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The NOR flash w25q128 denoted by JEDEC ID 0xef4018 actually represents
various models. From Winbond's website, I could only find 3 types of
them:
W25Q128JV-IQ/JQ
datasheet:https://www.winbond.com/resource-files/
w25q128jv%20revg%2004082019%20plus.pdf
W25Q128FV (SPI Mode)
datasheet: https://www.winbond.com/resource-files/
w25q128fv%20rev.m%2005132016%20kms.pdf
W25Q128BV
datesheet: https://www.winbond.com/resource-files/
w25q128bv_revh_100313_wo_automotive.pdf
According to the datasheets, all of these 3 types support BP(0,1,2) and
TB bits in the status register (SR), so it could reuse the flash
protection logic for ST Micro.
So it should be safe to add the SPI_NOR_HAS_LOCK and SPI_NOR_HAS_TB
flags to the w25q128 entry of spi_nor_ids table.
Signed-off-by: Su Baocheng <[email protected]>
[jagan: remove comments in spi-nor-ids.c]
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Add GD25LQ24C 64Mbit chip to spi-nor id table. This chip is used on
rk3399-gru-kevin:
=> sf probe
SF: Detected gd25lq64c with page size 256 Bytes, erase size 4 KiB, total 8 MiB
=> sf erase 0x600000 0x200000
SF: 2097152 bytes @ 0x600000 Erased: OK
=> sf test 0x700000 0x1000
SPI flash test:
0 erase: 52 ticks, 76 KiB/s 0.608 Mbps
1 check: 5 ticks, 800 KiB/s 6.400 Mbps
2 write: 14 ticks, 285 KiB/s 2.280 Mbps
3 read: 3 ticks, 1333 KiB/s 10.664 Mbps
Test passed
0 erase: 52 ticks, 76 KiB/s 0.608 Mbps
1 check: 5 ticks, 800 KiB/s 6.400 Mbps
2 write: 14 ticks, 285 KiB/s 2.280 Mbps
3 read: 3 ticks, 1333 KiB/s 10.664 Mbps
The values are the same as in Linux, except adjusted for the U-Boot
definition of INFO().
Signed-off-by: Alper Nebi Yasak <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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The set_speed() callback should configure the bus speed, make it so.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Stefano Babic <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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When copying to a u32 field we should use sizeof(u32) and not
sizeof(*u32) in memcpy.
On 64bit systems like cortina_presidio-asic-emmc_defconfig using
sizeof(*u32) leads to a buffer overrun.
Fixes: febe13b438b3 ("net: cortina_ni: Add eth support for Cortina Access CAxxxx SoCs")
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-By: Ramon Fried <[email protected]>
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ca_do_bch_correction() takes a random value from the stack and starts
counting bitflips from this value. Initialize the counter.
This passed unnoticed as the value is finally ignored in the call
hierarchy.
Fixes: 161df94b3c43 ("mtd: rawnand: cortina_nand: Add Cortina CAxxxx SoC support")
Signed-off-by: Heinrich Schuchardt <[email protected]>
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The values of left_edge[0] and right_edge[0] are overwritten before they
are used. Remove the superfluous assignments.
Fixes: 285b3cb939a8 ("dm: ddr: socfpga: fix gen5 ddr driver to not use bss")
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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In 8a8d24bd Simon dropped data from all the various _platdata calls
but it seems this wasn't caught for the RNG200 driver from when it
was posted to merged. This fixes that issue.
Fixes: 537f0018 (rng: Add iProc RNG200 driver)
Signed-off-by: Peter Robinson <[email protected]>
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VIRTIO_ID_MAX_NUM is the largest device ID plus 1. Therefore a device id
cannot be greater or equal to VIRTIO_ID_MAX_NUM. Fix the comparison
accordingly.
Fixes: 8fb49b4c7a82 ("dm: Add a new uclass driver for VirtIO transport devices")
Signed-off-by: Vincent Stehlé <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Bin Meng <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2021.04-rc3
qspi:
- Support for dual/quad mode
- Fix speed handling
clk:
- Add clock enable function for zynq/zynqmp/versal
gem:
- Enable clock for Versal
- Fix error path
- Fix mdio deregistration path
fpga:
- Fix buffer alignment for ZynqMP
xilinx:
- Fix reset reason clearing in ZynqMP
- Show silicon version in SPL for Zynq/ZynqMP
- Fix DTB selection for ZynqMP
- Rename zc1275 to zcu1275 to match DT name
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If zynqmp_qspi_set_speed() is called multiple times with the same speed,
then on the second call it will skip recalculating the baud_rate_val as
it assumes the speed is already configured correctly. But it will still
write the baud_rate_val to the configuration register and call
zynqmp_gqspi_set_tapdelay(). Because it skipped recalculating the
baud_rate_val, it will use the initial value of 0 . This causes the
driver to run at maximum speed which for many spi flashes is too fast and
causes data corruption.
Instead only write out a new baud_rate_val if we have calculated the
correct baud_rate_val.
This opens up another issue with the "if (speed == 0)", we don't save
off the new plat->speed_hz value when setting the baud rate on the
speed=0 path. Instead mimic what the Linux zynqmp gqspi driver does, and
have speed==0 just use the same calculation as a normal speed. That will
cause the baud_rate_val to use the slowest speed possible, which is the
safest option.
Signed-off-by: Brandon Maier <[email protected]>
CC: [email protected]
CC: [email protected]
CC: Ashok Reddy Soma <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Clean up error path in connection where priv->rxbuffers and priv->tx_bd are
allocated.
Signed-off-by: Michal Simek <[email protected]>
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Enable rx clock along with tx clock for versal platform. Use compatible
data to enable/disable clocks in the driver.
Signed-off-by: T Karthik Reddy <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
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Enable i2c controller clock from driver probe function
by calling clk_enable().
Signed-off-by: T Karthik Reddy <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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Add clock enable functionality in versal clock driver to enable
clocks from peripheral drivers using clk_ops.
Signed-off-by: T Karthik Reddy <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Add clock enable functionality in zynqmp clock driver to enable
clocks from peripheral drivers using clk_ops.
Signed-off-by: T Karthik Reddy <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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A lot of Xilinx drivers are checking -ENOSYS which means that clock driver
doesn't have enable function. Remove this checking from drivers and create
dummy enable function as was done for clk_fixed_rate driver by
commit 6bf6d81c1112 ("clk: fixed_rate: add dummy enable() function").
Signed-off-by: Michal Simek <[email protected]>
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Due to pointer arithmetic, "sizeof(u32) * ARCH_DMA_MINALIGN" is
subtracted. It seems that the original intention was to just subtract
ARCH_DMA_MINALIGN. Fix it.
Signed-off-by: Michael Walle <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Currently support for the Samsung serial port driver is part
of CONFIG_S5P which controls selection of several drivers for
the S5P family. Give it its own config option such that we
can use it on other SoCs as well.
Signed-off-by: Mark Kettenis <[email protected]>
Reviewed-by: Patrick Wildt <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Remove pmic_max8997/8 files about no-DM.
There are already existed max8997/8 as driver-model.
Signed-off-by: Jaehoon Chung <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic
- adds adc-keys button driver
- fix meson-saradc driver to get reference voltage
- add adc-keys test for sandbox
- enable adc-keys for VIM3 & VIM3L boards
- fix button.h build
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https://gitlab.denx.de/u-boot/custodians/u-boot-ti
- Fix ethernet on J721e
- Sync am335x DT nodes from Linux 5.9-rc7
- Minor Clock fixes
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https://gitlab.denx.de/u-boot/custodians/u-boot-video
- splash_source warning fix when building with 64-bit toolchains
- lq123p1jx31 and nv101wxmn51 compatible in simple panel driver
- remove not used mb862xx driver
- add Himax HX8238D panel driver
- s/video_uc_platdata/video_uc_plat/
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The previous version printed the same debug message for both the enable
and disable routines without highlighting whether you were enabling or
disabling the module. It is now clear whether you are enabling or
disabling the module.
Signed-off-by: Dario Binacchi <[email protected]>
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Signed-off-by: Rasmus Villemoes <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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Signed-off-by: Rasmus Villemoes <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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