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The dev_err() is used incorrectly and we don't need the driver
to state probe success.
Signed-off-by: Hal Feng <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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It's common that UARTs are bound and probed before U-Boot relocation, in
which case the UART's pincontroller and pinconfig must be probed first.
Let's apply DM_FLAG_PRE_RELOC to the driver, allow it to bind before
relocation.
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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It's common that UARTs are bound and probed before U-Boot relocation,
in which case the clocks of UART and UART's pincontroller must be
registered first. Let's apply DM_FLAG_PRE_RELOC to the driver, allowing
it to bind before relocation.
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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ethernet PHY (v4)"
Weijie Gao <[email protected]> says:
This patch adds PHY driver for MediaTek MT7987/MT7988 built-in 2.5Gb
ethernet PHY.
[trini: Change 'tristate' Kconfig to 'bool']
Link: https://lore.kernel.org/r/[email protected]
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The MediaTek MT7987/MT7988 SoCs features a built-in 2.5Gb PHY
connected to GMAC1. The PHY supports 10/100/1000/2500 Mbps
full-duplex only.
The PHY requires one or two firmware files. Firmware for MT7988 has
already been added to upstream: mediatek/mt7988/i2p5ge-phy-pmb.bin.
MT7987 has two firmware files which will be add to upstream later:
i2p5ge-phy-pmb.bin and i2p5ge-phy-DSPBitTb.bin.
Environment variable can be set for firmware data loading:
mt7987_i2p5ge_load_pmb_firmware for i2p5ge-phy-pmb.bin
mt7987_i2p5ge_load_dspbit_firmware for i2p5ge-phy-DSPBitTb.bin
mt7988_i2p5ge_load_pmb_firmware for i2p5ge-phy-pmb.bin
This driver allows dedicated weak functions to be overridden by
board to provide the firmware data:
mt7987_i2p5ge_get_fw() for MT7987
mt7988_i2p5ge_get_fw() for MT7988
To enable the PHY, add the following not to device tree:
ð1 {
status = "okay";
phy-mode = "xgmii";
phy-handle = <&phy15>;
phy15: ethernet-phy@15 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <15>;
phy-mode = "xgmii";
};
};
Signed-off-by: Sky Huang <[email protected]>
Signed-off-by: Weijie Gao <[email protected]>
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Associate PHY device with its device node specified by phy-handle
property. This makes it possible for PHY drivers to read dedicated
information to configure the PHY device.
Signed-off-by: Weijie Gao <[email protected]>
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request_firmware_into_buf_via_script()
Use cmd_process() to remove the length limit of script name used for
run_command().
Signed-off-by: Weijie Gao <[email protected]>
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request_firmware_into_buf_via_script()
It's important to return the actual firmware data size as some
firmware files may have no checksum and need the size as the only
way for firmware validation check.
Signed-off-by: Weijie Gao <[email protected]>
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Add STM32 OSPI driver, it supports :
- support sNOR / sNAND devices.
- Two functional modes: indirect (read/write) and memory-mapped (read).
- Single-, dual-, quad-, and octal-SPI communication.
- Single data rate (SDR).
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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Octo Memory Manager driver (OMM) manages:
- the muxing between 2 OSPI busses and 2 output ports.
There are 4 possible muxing configurations:
- direct mode (no multiplexing): OSPI1 output is on port 1 and OSPI2
output is on port 2
- OSPI1 and OSPI2 are multiplexed over the same output port 1
- swapped mode (no multiplexing), OSPI1 output is on port 2,
OSPI2 output is on port 1
- OSPI1 and OSPI2 are multiplexed over the same output port 2
- the split of the memory area shared between the 2 OSPI instances.
- chip select selection override.
- the time between 2 transactions in multiplexed mode.
- check firewall access.
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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Replace RIFSC check access APIs by grant/release access ones that handle
the RIF semaphores.
Signed-off-by: Gatien Chevallier <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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MUX_MMIO is needed by HBMC in SPL stage. Enable it at SPL as well
as u-boot proper stage.
Signed-off-by: Anurag Dutta <[email protected]>
Reviewed-by: Udit Kumar <[email protected]>
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In case the PHY exit callback reports failure, reset init_count to 0 anyway,
so the next attempt at PHY initialization might try to reinitialize the PHY
and restore it to normal operation.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Siddharth Vadapalli <[email protected]>
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Make sandbox_thermal_get_temp() static, since this is not called
outside of the driver. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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Sort the Makefile alphabetically. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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Greg Malysa <[email protected]> says:
Between 2025.07 and 2025.10 many header dependency chains were improved,
but this exposed implicit header usage in several of our drivers. This
wasn't discovered before or included in the original fixes because our
drivers are not yet used by any mainline-supported boards, so build
tests did not find them. This series addresses the two build failures
I've encountered while rebasing our work onto 2025.10 and continuing to
prepare the next submission of our board files.
Link: https://lore.kernel.org/r/[email protected]
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As part of the header dependency cleanup between 2025.07 and 2025.10, an
implicit route to obtain SZ_128M from linux/sizes.h was removed. This
adds an explicit reference to linux/sizes.h to fix build failures for
this driver.
Signed-off-by: Greg Malysa <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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Following header dependency cleanups, an implicit dependence on env.h
was exposed in dwc_eth_qos_adi. However because this driver is not (yet)
enabled in any defconfigs, build tests did not identify the missing
header. This adds the missing #include so that the driver builds
correctly when enabled.
Signed-off-by: Greg Malysa <[email protected]>
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The ADP5587 is a simpler version of the ADP5588. The ADP5588 can
configure two pins, C8 and C9, as GPIOs or light sensors. The ADP5587
does not include the light sensors.
Signed-off-by: Philip Molloy <[email protected]>
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The layout of SYSCFG_ETHnCR on STM32MP25xx is slightly different yet again.
Add missing swizzling to program the correct register with the correct content.
Fixes: 20afca89ed53 ("net: dwc_eth_qos: add support of stm32mp2 platform")
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Christophe ROULLIER<[email protected]>
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The clk_register_composite() does clk_resolve_parent_clk() look up,
which requires valid udevice pointer. Do not pass NULL, pass a valid
device pointer to prevent hang on registering ck_usbo_48m clock on
STM32MP13xx.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Anshul Dalal <[email protected]> says:
On various TI's K3 platforms boot failure was observed on SPI NOR since the
commit 5609f200d062 ("arm: Kconfig: enable LTO for ARCH_K3"). This issue was
root caused to stack corruption by the 'udma_transfer' function. Where the local
variable 'paddr' of type 'dma_addr_t' was being written to as a 64-bit value
which overwrote the stack frame of the caller (dma_memcpy) as only 32-bits had
been reserved for paddr on the stack, specifically the r4 register in the frame
of dma_memcpy was being overwritten with a 0.
drivers/dma/ti/k3-udma.c:2192:
int udma_transfer(...)
{
...
dma_addr_t paddr = 0;
...
/* paddr was written to as 64-bit value here */
udma_poll_completion(uc, &paddr);
}
drivers/dma/dma-uclass.c:234:
int dma_memcpy(...)
{
dma_addr_t destination;
dma_addr_t source;
int ret;
...
/* This call resolves to udma_transfer */
ret = ops->transfer(...);
...
dma_unmap_single(destination, ...);
dma_unmap_single(...);
return ret;
}
Enabling LTO changed how gcc mapped local variables of dma_memcpy to CPU
registers, where earlier the bug was hidden since the overwritten register
'r4' was allotted to 'ret' but was allotted to 'destination' once LTO was
enabled. And since the overwritten value was 0, the bug remained undetected
as it just meant ret was 0, but having 'destination' set to 0 caused
dma_unmap_single to fail silently leading to boot failures.
The fix entails enabling DMA_ADDR_T_64BIT which changes dma_addr_t from u32 to
u64 for the R5 SPL thus reserving enough space for 'paddr' to prevent the
overflow.
Link: https://lore.kernel.org/r/[email protected]
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dma_addr_t is used to store any valid DMA address which might not
necessarily be the same size as host architecture's word size. Though
various typecasts in k3's dma and usb driver expect dma_addr_t to be the
same size as the word size.
This leads the compiler to throw a "cast from pointer to integer of
different size" warning when the condition is not met, for example when
enabling CONFIG_DMA_ADDR_T_64BIT for the R5 core.
Therefore this patch fixes the typecasts by using 'uintptr_t' as an
intermediary type which is guaranteed to be the same size as void* on
the host architecture. Thus, eliminating the compiler warning.
Signed-off-by: Anshul Dalal <[email protected]>
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QEMU allows to specify the logical block size via parameter
logical_block_size of a virtio-blk-device.
The communication channel via virtqueues remains based on 512 byte blocks
even if the logical_block_size is larger.
Consider the logical block size in the block device driver.
Reported-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Heinrich Schuchardt <[email protected]>
Tested-by: Emil Renner Berthing <[email protected]>
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Replace uint8_t/uint32_t with u8/u32 to match U-Boot style
(checkpatch PREFER_KERNEL_TYPES). No functional change.
Signed-off-by: Bhimeswararao Matsa <[email protected]>
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Replace use of uninitialized variable with the PCI device number
in an error message as this is what we use elsewhere to derive
the PCIe port number. Use ofnode_read_pci_addr() to read the
PCI address of the node and derive the device number from that.
Signed-off-by: Mark Kettenis <[email protected]>
Reported-by: Andrew Goodbody <[email protected]>
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Initialize the actread variable to prevent undefined behavior
that can occur if the variable is used before being assigned a
value.
This will help to prevent potential issues, especially if
actread is used (e.g., read, incremented, or returned) before
being explicitly set elsewhere in the code.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
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The MAX31331 was not correctly updating the seconds when
setting the time and would return the seconds previously set.
Like the MAX31343, a delay needs to be added after setting the
time. Wait one second after writing so that the date command shows the
correct time.
Reviewed-by: Chris Packham <[email protected]>
Reviewed-by: Bruce Adams <[email protected]>
Signed-off-by: Ben Hoelker <[email protected]>
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Prepare v2025.10-rc4
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Add a MAINTAINERS entry for the DesignWare XGMAC network driver to
ensure future patches are properly routed for review and support.
Signed-off-by: Boon Khai Ng <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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- Fix issues reported by smatch
- exynos4210-origen cleanups
- e850-96 improvements
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In spi_rx_tx there comes a test for execution of a code block that
allows execution if rxp is not NULL or stopping is true. However all the
code in this block relies on rxp being valid so allowing entry just if
stopping is true does not make sense. So remove this from the test
expression leaving just a NULL check for rxp.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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In rzg2l_pinconf_set and rzg2l_get_pin_muxing if the call to
rzg2l_selector_decode fails then the variable pin may not have been
assigned to. Remove the use of pin from the error message. Also update
the error message to show the invalid selector used instead of port
which will be the error code returned.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Reviewed-by: Paul Barker <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-rockchip
CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/27522
- New Board support:
rk3588 Xunlong Orange Pi 5 Ultra;
rk3588s GameForce Ace;
rk3576 ArmSoM Sige5;
- rk3328 soc fixes;
- usb controller and phy fixes;
- new rk3328 ddr timing;
- other board level updates;
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Enable support for Exynos850 SoC in DWC3 host glue layer driver.
Signed-off-by: Sam Protsenko <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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In exynos7420_peric1_get_rate the variable ret is declared as an
'unsigned int' but is then used to receive the return value of
clk_get_by_index which returns an int. The value of ret is then tested
for being less than 0 which will always fail for an unsigned variable.
Fix this by declaring ret as an 'int' so that the test for the error
condition is valid.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Remove unnecessary whitespace before '\n' in trace printf
format strings (checkpatch warning QUOTED_WHITESPACE_BEFORE_NEWLINE).
No functional change intended.
Signed-off-by: Bhimeswararao Matsa <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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In sdhci_iproc_execute_tuning the variable tuning_loop_counter is
unsigned and therefore will always fail the test for it being less than
0. Fix this by changing the variable type to be s8.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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PCA9450 PMIC supports reading the reset status from the PWRON_STAT
register. Bits 7-4 give indication of the PMIC reset cause:
- PWRON (BIT7) - Power ON triggered by PMIC_ON_REQ input line,
- WDOGB (BIT6) - Boot after cold reset by WDOGB pin (watchdog reset),
- SW_RST (BIT5) - Boot after cold reset initiated by the software,
- PMIC_RST (BIT4) - Boot after PMIC_RST_B input line trigger.
Add support for reading reset status via the sysreset framework in a
convenient printable format.
Signed-off-by: Primoz Fiser <[email protected]>
Reviewed-by: Paul Geurts <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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The family of PCA9450 PMICs have the ability to perform system resets.
Restarting via PMIC is preferred method of restarting the system as all
the peripherals are brought to a know state after a power-cycle. The
PCA9450 features a cold restart procedure which is initiated by an I2C
command 0x14 to the SW_RST register.
Support in Linux for restarting via PCA9450 PMIC has been added by
Linux commit 6157e62b07d9 ("regulator: pca9450: Add restart handler").
Now add support for it also in the U-Boot via sysreset framework.
Signed-off-by: Primoz Fiser <[email protected]>
Reviewed-by: Paul Geurts <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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All u-boot users now use maxim,max8997-pmic instead, as does Linux's
DTSes, so we can now safely drop the maxim,max8997 compatible.
Signed-off-by: Henrik Grimler <[email protected]>
Reviewed-by: Anand Moon <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Linux's DTSes uses maxim,max8997-pmic, so check for this compatible
as well so that max8997 pmic driver can support both u-boot and
Linux's DTSes.
Signed-off-by: Henrik Grimler <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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To make the help message slightly easier to understand.
Signed-off-by: Henrik Grimler <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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All devicetrees that use s2mps11 driver have been converted to use
regulators { };, so we can safely drop the voltage-regulators fallback
check.
Signed-off-by: Henrik Grimler <[email protected]>
Reviewed-by: Anand Moon <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Linux's DTSes uses regulators { }; while u-boot's DTSes uses
voltage-regulators { };. Look for regulators, and fallback to
voltage-regulators if not found, so that both type of DTSes can be
used with the driver.
Signed-off-by: Henrik Grimler <[email protected]>
Reviewed-by: Anand Moon <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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There are two ways to set the output voltage of the LD05
regulator. First by writing to the voltage selection registers
and second by toggling the SD_VSEL signal.
Usually board designers connect SD_VSEL to the VSELECT signal
controlled by the USDHC controller, but in some cases the
signal is hardwired to a fixed low level (therefore selecting
3.3V as initial value for allowing to boot from the SD card).
In these cases, the voltage is only determined by the value
of the LDO5CTRL_L register. Introduce a property
nxp,sd-vsel-fixed-low to let the driver know that SD_VSEL
is low and there is no GPIO to actually get that
information from dynamically.
This is equivalent to the following change in Linux:
c8c1ab2c5cb7 ("regulator: pca9450: Handle hardware with fixed SD_VSEL for LDO5")
Signed-off-by: Frieder Schrempf <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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For LDO5 we need to be able to check the status of the SD_VSEL input in
order to know which control register is used. Read the status of the
SD_VSEL signal via GPIO and use the correct register accordingly.
To use this, the LDO5 node in the devicetree needs the sd-vsel-gpios
property to reference the GPIO that is used to read back the SD_VSEL
status internally. Please note that the SION bit in the IOMUX must be
set if the signal is muxed as VSELECT and controlled by the USDHC
controller.
This is equivalent to the following change in Linux:
3ce6f4f943dd ("regulator: pca9450: Fix control register for LDO5")
Signed-off-by: Frieder Schrempf <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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The LDO5 regulator has two configuration registers, but only
LDO5CTRL_L contains the bits for enabling/disabling the regulator.
This is equivalent to the following change in Linux:
f5aab0438ef1 ("regulator: pca9450: Fix enable register for LDO5")
Fixes: 326337fb005f ("pmic: pca9450: Add regulator driver")
Signed-off-by: Frieder Schrempf <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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This reverts commit 2add0511757e2c5897a88b57c5ea8c912140e60f.
It turns out that all boards using the PCA9450 actually have the
SD_VSEL input connected to the VSELECT signal of the SoCs SD/MMC
interface. Therefore we don't need manual control for this signal
via GPIO and there aren't any users.
This is equivalent to the following change in Linux:
c73be62caabb ("Revert "regulator: pca9450: Add SD_VSEL GPIO for LDO5"")
Signed-off-by: Frieder Schrempf <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Andrew Goodbody <[email protected]> says:
Smatch reported some issues in the regulator drivers, mostly repeated
instances of testing an unsigned variable for being negative but also an
expression needing parenthesis to be interpreted as expected.
[trini: Drop 5/6 for now due to changes being requested on review]
Link: https://lore.kernel.org/r/[email protected]
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