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Update the firmware driver UFS APIs zynqmp_pm_ufs_* to directly
read/write to the pmc_iou_slcr and efuse_cache registers. Replace
these raw reads/writes with the xilinx_pm_request() API with the
correct arguments once the PM related changes are done.
Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/ee2d1ad2e07e96f1948ab6ffe8f3c50a3b8f9be9.1742462001.git.michal.simek@amd.com
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Add useful default debug uart values for all Versal platforms to simplify
and speed up debug uart enabling.
The similar change has been done for Zynq/ZynqMP by commit ad55d99e3cc3
("serial: Setup serial base and freq for zynq/zynqmp").
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/86edf3dbb6de16337aac36f5121f306f83149fc0.1741868624.git.michal.simek@amd.com
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Add support for flash device reset via OSPI controller
instead of using GPIO, as OSPI IP has device reset
feature on Versal Gen2 platform. Also add compatible
string for Versal Gen2 platform.
Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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Added extended support for retrieving the PMC muti boot mode
register via the firmware interface, which is preferred when
U-Boot runs in EL2 and cannot directly access PMC registers
via raw reads. Ideally, all secure registers should be accessed
via xilinx_pm_request(). Introduced the secure
zynqmp_pm_get_pmc_multi_boot_reg() call, which uses
xilinx_pm_request() to read the PMC multi boot mode register.
BootROM increments the MultiBoot register (PMC_MULTI_BOOT) read
address offset by 32 KB and retries. For SD and eMMC boot modes,
it can search up to 8191 FAT files for the identification string.
A 13-bit mask (0x1FFF) is applied to PMC_MULTI_BOOT_MASK to obtain
the correct values in BootROM.
Signed-off-by: Prasad Kummari <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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Added extended support for retrieving the boot mode register
via the firmware interface, which is preferred when U-Boot
runs in EL2 and cannot directly access CRP registers via raw
reads. Ideally, all secure registers should be accessed via
xilinx_pm_request(). Introduced the secure zynqmp_pm_get_bootmode_reg()
call, which uses xilinx_pm_request() to read the boot mode register.
When CONFIG_ZYNQMP_FIRMWARE is enabled, the secure
zynqmp_pm_get_bootmode_reg() call is used; otherwise,
direct raw reads are performed in the case of mini U-Boot.
Signed-off-by: Prasad Kummari <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-tpm
A small fix for the cr50 which is a TPM but doesn't support all
the TPM functionality. Since it deviates from our normal TIS compliant
TPMs it can't be started twice since running the selftests twice hangs.
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When FIT image with multiple dtbs are involved for R5 boot process,
R5 SPL starts off with the first instance of dtb to probe the
eeprom, then once we have identified the type of board, invocation
of setup_multi_dtb_fit will replace the gd->fdt_blob with the proper
board dtb match. However, when we do this, two things happen:
a) Prior to the invocation of setup_multi_dtb_fit, as part of the eeprom
discovery process, i2c controller device is already probed and marked
as exclusive with the match of the very first tisci match (from the
original boot dtb). This list is stored in the info->dev_list of the
first probe.
b) When the second dtb is loaded, tisci is probed again (since this is a
new node) and the new info->dev_list is empty.
At this stage, the exclusive devices such as i2c instances used to
probe the board information is left in the old info->dev_list that is
no longer used actively by the system using the replaced dtb.
As a result of this, the cleanup we intend to do with
ti_sci_cmd_release_exclusive_devices is no longer complete and
leaves the instances such as i2c for eeprom marked used as we scan just
the new info->dev_list.
This creates a problem when Device Manager(DM) firmware starts up later
on in the boot process and identifies that this instance of i2c is
already marked active, so it assumes this can no longer be controlled
by software and is marked internally as reserved and HLOS can no
longer control these instances. This defeated the purpose of
ti_sci_cmd_release_exclusive_devices.
NOTE: This scheme works just fine if the FIT has just a single dtb as
the info->dev_list is upto date.
To fix this, let us make ti_sci_cmd_release_exclusive_devices scan the
all registrations of tisci instances and cleanup all exclusive devices
that have ever been registered.
As part of this, change the prototype of release_exclusive_devices to
drop the handle since that has no further meaning now.
Though this issue was identified on AM64-sk, this can be present in
other builds which use multi-fit-dtb for R5 SPL startup.
Fixes: 9566b777ae0a ("firmware: ti_sci: Add a command for releasing all exclusive devices")
Signed-off-by: Nishanth Menon <[email protected]>
Reviewed-by: Dhruva Gole <[email protected]>
Reviewed-by: Neha Malcom Francis <[email protected]>
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The tpm_auto_start() function is used in tests and assumes that it can
open the TPM even if it is already open and a locality claimed. The cr50
driver does not use the common TPM2 TIS code so lacks a check for the
is_open field of struct tpm_chip and in fact it doesn't use that struct.
Add an equivalent check to cr50_i2c_open().
This fixes all init sequences on that TPM -- e.g 'tpm init && tpm init'
or 'tpm autostart && tpm init' used to hang
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
Signed-off-by: Ilias Apalodimas <[email protected]>
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UART-A can be exposed through uSD, this was tested on Transformer T20
but should work on all Ventana-based boards.
TX is exported on SDD pingroup corresponding to uSD CLK pin
RX is exported on SDB which is CMD pin in uSD slot
Signed-off-by: Artur Kowalski <[email protected]>
Reviewed-by: Svyatoslav Ryhel <[email protected]>
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Applies same logic to general Tegra pincontrol driver as is done to Tegra20
by commit:
a35bf832d70 ("pinctrl: tegra20: detect unknown/invalid pin/func
configurations")
Suggested-by: Artur Kowalski <[email protected]>
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Tegra20 driver doesn't know about some pin configurations and even about
some pins. In case when pin configuration is unknown the pin would be
muxed to whatever is under function 0, in case when pin itself is
unknown, it could cause out-of-bounds array access in pinmux_set_func
and pinmux_set_pullupdown.
Signed-off-by: Artur Kowalski <[email protected]>
Reviewed-by: Svyatoslav Ryhel <[email protected]>
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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The LM3532 is a 500-kHz fixed frequency asynchronous boost converter which
provides the power for 3 high-voltage, low-side current sinks. The device
is programmable over an I2C-compatible interface and has independent
current control for all three channels.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Add support for the LCD panel module used in Motorola Atrix 4G or Droid X2.
Exact panel vendor and model are unknown. The panel has a 540x960 (qHD)
resolution and uses 24 bit RGB per pixel.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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CPCAP has a dedicated interrupt for power button. Implement this to have
more input control over the devices.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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The driver provides regulator set/get voltage and enable/disable functions
for CPCAP PMIC.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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The CPCAP is a Motorola/ST-Ericsson creation, a multifunctional IC whose
main purpose was power control. It was used in a wide variety of Motorola
products, both Tegra and OMAP based. The most notable devices using this
PMIC are the Motorola Droid 4, Atrix 4G, and Droid X2.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Fix DC and DSI config names to reflect more generic nature of existing
Tegra video drivers.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Dir name is enough.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Place Tegra124 SOR and eDP implenetation into common Tegra driver folder
until it is integrated into existing setup.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Since this set of drivers suports four Tegra SoC generations, lets name it
just 'tegra'.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Reviewed-by: Peter Robinson <[email protected]>
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Existing Tegra30 DSI configuration is fully compatible with Tegra20.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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GPIO reset and power-off functionality depends on device tree data, which
is often absent in SPL or TPL. To address this, incorporate PHASE_ into the
config option and add Kconfig option or each phase.
Adjust SYSRESET_GPIO and POWEROFF_GPIO uses to address possible
regressions.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Add missing configuration of chip select polarity. Default polarity is LOW,
which satisfies most cases but some devices require HIGH polarity and will
not work.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Tom Rini <[email protected]> says:
This series switches to always using $(PHASE_) in Makefiles when
building rather than $(PHASE_) or $(XPL_). It also starts on documenting
this part of the build, but as a follow-up we need to rename
doc/develop/spl.rst and expand on explaining things a bit.
Link: https://lore.kernel.org/r/[email protected]
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It is confusing to have both "$(PHASE_)" and "$(XPL_)" be used in our
Makefiles as part of the macros to determine when to do something in our
Makefiles based on what phase of the build we are in. For consistency,
bring this down to a single macro and use "$(PHASE_)" only.
Signed-off-by: Tom Rini <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-snapdragon
Qualcomm changes for v2025.07:
CI: https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/pipelines/25653
There's been a surprising amount of activity lately on the Qualcomm
side with the two oldest boards getting some fresh attention and a lot
of cleanup and polish going on across the board.
* SDM660 gets USB phy fixes and a pinctrl driver
* The recently added SA8775P/QCS9100 SoC gets a pinctrl driver
* The Qualcomm pinctrl driver now handles reserved pins correctly,
fixing crashes on some boards when running "gpio status -a"
* OF_UPSTREAM_BUILD_VENDOR is enabled in qcom_defconfig
* SDM845 and SC7280 get missing clocks added (since we're now stricter
about those). This gets USB working more reliably in more cases.
* DM_USB_GADGET is enabled for all boards using DWC3 and fasbtoot is
enabled too
* A bug in the livetree fixup code is fixed (making USB work on a lot
more platforms)
* Button label lookup is made case insensitive* bootretry becomes more dynamic, allowing it to be hijacked to make a
"persistent" boot menu that allows dropping to U-Boot shell later on
* A new qcom-phone.config fragment is added along with a phone-specific
default environment and phone-specific debugging/bringup docs. These
make U-Boot more usable on devices without a serial port or keyboard.
* The db820c gets fixed up and updated documentation
* The db410c also gets some love and modernisation as well as a new
reviewer.
* A new driver is added for the USB VBUS regulator found on various
Qualcomm PMICs
* The Qualcomm SPMI driver gets some fixes and cleanup for SPMI v5 and
v7 support.
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/25652
- Add i.MX8MP LDB support.
- Various phycore-imx93 environment improvements.
- Add support for Toradex SMARC iMX8MP.
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https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request efi-2025-07-rc1
CI:
* https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/25648
Documentation:
* Update authenticated capsules documentation
UEFI:
* Add support for loading FIT images including initrd
- efi_loader: efi_load_initrd: provide a memory mapped initrd
- efi_loader: binary_run: register an initrd
- bootm: add support for initrd in do_bootm_efi
* efi_selftest: remove un-needed NULL checks
* efi: Fix efiboot for payloads loaded from memory
* Print extra information from the bootmgr
* Move public cert for capsules to .rodata
* Set EFI capsule dfu_alt_info env explicitly
* Make FDT extra space configurable
* Install the ACPI table from the bloblist
* Handle GD_FLG_SKIP_RELOC
* Handle malloc() errors
Others:
* acpi: select CONFIG_BLOBLIST
* smbios: select CONFIG_BLOBLIST
* xilinx: dfu: Fill directly update_info.dfu_string
* cmd: fwu: Dump custom fields from mdata structure
* board: remove capsule update support in set_dfu_alt_info()
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https://source.denx.de/u-boot/custodians/u-boot-mmc
CI: https://source.denx.de/u-boot/custodians/u-boot-mmc/-/pipelines/25640
- Support Sandisk and Micron eMMC BOOT/RPMB hardware partition resizing
- Optimize eMMC erasing time
- Simplify poll CD logic
- Fix possible Synchronous Abort for sdhci
- Kconfig dependencies fix
- Minor code update, return fail if mmc_complete_init, avoid uniniting twice
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Some Qualcomm boards feature reserved ranges of pins which are protected
by firmware. Attempting to read or write any registers associated with
these pins results the board resetting.
Add support for parsing these ranges from devicetree and ensure that the
pinctrl and GPIO drivers don't try to interact with these pins.
Signed-off-by: Neil Armstrong <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Link: https://lore.kernel.org/r/20250410-topic-sm8x50-pinctrl-reserved-ranges-v2-1-654488392b9a@linaro.org
Signed-off-by: Caleb Connolly <[email protected]>
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This function is already doing a fuzzy match, since there are no
guarantees that a given label is unique.
Ignoring case makes it much easier to catch "Volume down" or "Volume
Down" in board-agnostic code.
Tested-by: Danila Tikhonov <[email protected]> # google-sunfish
Tested-by: Jens Reidel <[email protected]> # xiaomi-davinci
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Caleb Connolly <[email protected]>
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Boards using gpio-keys for volume buttons label them "Volume Down",
let's match that here, and make the power button nicer too.
This simplifies configuring button_cmds in a board-agnostic way.
Tested-by: Danila Tikhonov <[email protected]> # google-sunfish
Tested-by: Jens Reidel <[email protected]> # xiaomi-davinci
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Caleb Connolly <[email protected]>
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Add support for TLMM pin controller block (Top Level Mode
Multiplexer) on SDM630/660 SoCs, with support for special pins.
Correct pin configuration is required for working debug UART
and eMMC/SD cards.
SDM630 and SDM660 TLMM blocks are the same.
Signed-off-by: Alexey Minnekhanov <[email protected]>
Reviewed-by: Caleb Connolly <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Caleb Connolly <[email protected]>
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When a special pin is output only, the current code would return 0,
but if the pin is output only we can get the output value.
Try to return the output value and in all the other cases return
an error instead of 0.
Fixes: f9bb539460d ("gpio: msm: add support for special pins")
Signed-off-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/20250401-topic-sm8x50-msm-gpio-special-fixes-v1-2-a1148a02bb16@linaro.org
Signed-off-by: Caleb Connolly <[email protected]>
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The get_function callback wrongly returns 0 for special pins,
return the appropriate pin function by probing into the special
pins data fields to find if the pin is gpio capable.
Fixes: f9bb539460d ("gpio: msm: add support for special pins")
Signed-off-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/20250401-topic-sm8x50-msm-gpio-special-fixes-v1-1-a1148a02bb16@linaro.org
Signed-off-by: Caleb Connolly <[email protected]>
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Since commit 53d5a221632e ("emulation: Use bloblist to hold tables")
`make qemu-riscv64_smode_defconfig acpi.config && make` fails with
drivers/misc/qfw_smbios.c:93:(.text.qfw_evt_write_smbios_tables+0xe):
undefined reference to `bloblist_add'
Build with bloblist support.
Fixes: 53d5a221632e ("emulation: Use bloblist to hold tables")
Reviewed-by: Ilias Apalodimas <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Heinrich Schuchardt <[email protected]>
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i.MX95 System Manager uses interrupt driven communication which requires
the caller to set Bit[0] of channel flags to 1. When transmission
completes and the previous general purpose interrupt has been processed
by the other core, i.MX95 System Manager will set General Purpose
Interrupt Control Register (GCR). U-Boot polls General-purpose Status
(GSR) to check if the operation is finished.
Signed-off-by: Viorel Suman <[email protected]>
Signed-off-by: Alice Guo <[email protected]>
Reviewed-by: Ye Li <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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resizing
Current mmc bootpart-resize command only support Samsung eMMC BOOT/RPMB
hardware partition resizing. Add Sandisk and Micron eMMC BOOT/RPMB hardware
partition resizing support. The commands and parameters for resizing
partitions are different for each manufacturer. Select the corresponding
function according to CID.
Signed-off-by: Luke Wang <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Each MMC device has a child which ihs a block device. At present we call
mmc_deinit() when the block device is removed.
But the MMC struct (i.e. struct mmc) is attached to the MMC's device,
not its child.
So at present, when an MMC device is removed, mmc_deinit() is called
twice, once for the MMC device and once for its block device. This
results in a double call to cyclic_unregister().
Fix this by adding a 'remove' method to the uclass and calling
mmc_deinit() from there.
Also drop the call to device_probe() within the block-device's probe()
method. The device is already in the process of being probed, so this
call does nothing.
Signed-off-by: Simon Glass <[email protected]>
Fixes: c822c1a50bd ("mmc: call device_probe() after scanning")
Signed-off-by: Peng Fan <[email protected]>
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When MMC_SDHCI_SDMA=y or MMC_SDHCI_ADMA=y and PIO mode is used
dma_unmap_single() is called on an unmapped address, 0x0. This may
result in a Synchronous Abort:
## Checking hash(es) for Image atf-1 ... sha256+ OK
CMD_SEND:16
ARG 0x00000200
MMC_RSP_R1,5,6,7 0x00000900
CMD_SEND:18
ARG 0x00004005
"Synchronous Abort" handler, esr 0x96000147
elr: 00000000400015bc lr : 0000000040012b4c
x 0: 0000000000008000 x 1: 0000000000092600
x 2: 0000000000000040 x 3: 000000000000003f
x 4: 0000000000000030 x 5: 0000000000000001
x 6: 0000000000000001 x 7: 0000000000000000
x 8: 000000000000000a x 9: 0000000000000090
x10: 0000000043dffc68 x11: 0000000043c00440
x12: 0000000043c00440 x13: ffffffffbfe00000
x14: 000000000000031c x15: 0000000240000000
x16: 000000004001145c x17: 0000000000000032
x18: 0000000043dffef0 x19: 0000000043c00000
x20: 0000000043dffbc8 x21: 0000000000000000
x22: 00000000000f3d95 x23: 0000000000000002
x24: 0000000000000493 x25: 0000000000092600
x26: 0000000000000001 x27: 0000000000000001
x28: 0000000000000008 x29: 0000000043dffab0
Code: d2800082 9ac32042 d1000443 8a230000 (d5087620)
Resetting CPU ...
resetting ...
Fix this by only dma_unmap_single() when DMA mode is used and
sdhci_prepare_dma() has been called to map host->start_addr.
Signed-off-by: Jonas Karlman <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Per JESD84-B51 6.6.9 Erase:
The host can erase a contiguous range of Erase Groups. Starting the erase
process is a three steps sequence. First the host defines the start address
of the range using the ERASE_GROUP_START (CMD35) command, next it defines
the last address of the range using the ERASE_GROUP_END (CMD36) command and
finally it starts the erase process by issuing the ERASE (CMD38) command
with argument bits set to zero. See Table 11 for the arguments supported by
CMD38. The address field in the erase commands is an Erase Group address,
in byte units for densities up to 2GB, and in sector units for densities
greater than 2GB. The Device will ignore all LSB's below the Erase Group
size, effectively rounding the address down to the Erase Group boundary.
So choose 2GB bytes as check condition.
If the erase size is larger that 2GB, use 2GB to avoid breaking non high
capacity cards. If erase size is less than 2GB and larger than a grp, use
'grpcnt * mmc->erase_grp_size' to cover all the sectors, else use
the number of sectors.
With test erasing 20GB eMMC
board: Evk_8ulp Evk_8mm Evk_8mn Evk_8mp Mek_8qxpc0 Mek_8qm
kingston sandisk
before: 37.683s 112.738s 129.365s 28.238s 112.605s 500.470s 490.708s
after: 0.093s 0.111s 0.951s 0.080s 0.121s 6.960s 6.915s
Tested-by: Faqiang Zhu <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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In case mmc_complete_init() returns error, exit from mmc_init()
without possibly calling cyclic_register(), which at that point
would be undesired.
Signed-off-by: Marek Vasut <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Simplify 90cc07fd786d ("mmc: Poll CD in case cyclic framework is enabled")
according to suggestions by Rasmus. The struct cyclic_info is zero-size in
case CONFIG_CYCLIC is not enabled and does not add any size to struct mmc,
so it can unconditionally be part of that structure. This allows clean up
of all the other conditionals in mmc.c which can now be unconditionally
present, as they also add no extra space.
Suggested-by: Rasmus Villemoes <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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The option MMC_SDHCI_ADMA_FORCE_32BIT is only tested or used when
MMC_SDHCI_ADMA or SPL_MMC_SDHCI_ADMA is enabled. And for
MMC_SDHCI_ADMA_64BIT the same is true except we also require
MMC_SDHCI_ADMA_FORCE_32BIT to be disabled.
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
Acked-by: Peng Fan <[email protected]>
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UFS devices uses the block and scsi frameworks. Enable UFS erase
support by adding erase support to SCSI.
Signed-off-by: Varadarajan Narayanan <[email protected]>
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Add support for the LCD interfaces (LCDIF1/2). When probed, these
interfaces request numerous clocks and power domains, attach the bridge
and look for a panel in order to retrieve its capabilities and
properties.
There is a similar existing driver in the upper folder for other i.MX
targets, I discovered this driver a bit late. It is not targeting the
i.MX8MP and I have no idea how different can the LCDIF be on this SoC,
but I did not manage to get it work, especially because it is not fully
compliant with the device-model, especially on the clocks/power
management side which is all ad-hoc. This is normal though, it was
contributed more than ten years ago.
Signed-off-by: Miquel Raynal <[email protected]>
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Add support for the LVDS Display Bridge (LDB) found on i.MX8MP.
When attached, the bridge driver looks for panels connected to one of
its two outputs and adapts its own configuration to use them. There is
currently no support for merged/split displays.
Note regarding the clock configuration:
The LDB output clock should be absolutely identical to the LCDIF output
clock so both blocks can talk to each other synchronously. However, the
LDB clock has an internal divisor of 7 (respectively 3.5 in dual
configuration) which means the LDB input clock must be explicitly set
once we know the configuration.
This driver was tested on i.MX8MP using a single panel connected to the
LVDS2 interface.
Signed-off-by: Miquel Raynal <[email protected]>
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The IPUv3 is one IP part of the imx world, there are others, and
selecting the whole imx/ folder based on such a specific Kconfig symbol
is sub-optimal. Let's always enter the imx/ folder, and then selectively
compile parts of the folder based on the configuration.
Signed-off-by: Miquel Raynal <[email protected]>
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This block delivers power and clocks to the whole display and rendering
pipeline.
Signed-off-by: Miquel Raynal <[email protected]>
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Add support for the i.MX8 MEDIAMIX domain which is driving the power
over the whole display/rendering pipeline.
Signed-off-by: Miquel Raynal <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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