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The hardware denies any access from the U-Boot non-secure world to the
secure-protected pins. Hence, prevent any driver to request such a pin.
Signed-off-by: Fabien Dessenne <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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Christian Marangi <[email protected]> says:
This small series consolidate header usage of mdio-mt7531-mmio driver
and improve usage in preparation for support of OF PHY autoprobe.
This driver is still not used (as it will be used by AN7581/AN7583)
in the OF mode (it's used by MT7988 for the MDIO functions)
For OF PHY to be correctly autoprobed, the MDIO driver needs to attached
to the MDIO node (the parent of the PHY nodes)
With such change the MDIO driver can be binded with the MDIO node instead
of the switch node as previously required.
Link: https://lore.kernel.org/r/[email protected]
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The MDIO node is ALWAYS a parent of the MT7531 switch node and the MDIO
registers are in the MT7531 register space (in the context of MT7988
it's all memory-mapped)
With these assumption, we can simplify and permit better usage of PHY OF
automatic probing by binding the mt7531-mdio-mmio driver with the MDIO
node instead of the switch node.
For OF PHY to be correctly autoprobed, the MDIO driver needs to attached
to the MDIO node (the parent of the PHY nodes).
The driver will reach the parent node (the switch node) and will parse
the register address from there.
Signed-off-by: Christian Marangi <[email protected]>
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Instead of having duplicate priv struct for mdio-mt7531-mmio driver in
both driver and header, use the one exposed by the header directly.
This make sure we have consistent priv struct if the driver will be
updated in the future.
Signed-off-by: Christian Marangi <[email protected]>
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Prepare v2026.04-rc3
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This patch adds support for the ISSI IS25WP02GG QSPI NOR flash device.
Tested on the Versal VMK180
board in dual-parallel QSPI configuration.
Signed-off-by: jeffrey yu <[email protected]>
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This part is an FRAM, but can be used through the spi-nor generic code.
Signed-off-by: [email protected]
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i.MX8QXP rev C.0 requires boot container stored at offset 0KB
for eMMC, while i.MX8QXP pre C.0 requires boot container stored
at offset 32KB for eMMC.
To use one U-Boot binary to support different chip revisions,
introduce fb_mmc_get_boot_offset() to allow override the default
offset when writing to eMMC boot partitions.
This enables support for devices with non-standard boot partition
layouts, such as those requiring an offset for correct bootloader
placement.
Signed-off-by: Adrian Freihofer <[email protected]>
Signed-off-by: Heiko Schocher <[email protected]>
Reviewed-by: Mattijs Korpershoek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mattijs Korpershoek <[email protected]>
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single-word support"
Niko Mauno <[email protected]> says:
In this series, we first introduce a clean-up where we switch to use
predefined bit masks instead of hard-coded values for count and magic
halves in the single-word (32-bit) boot count scheme.
Then we fix a case of missing boot count value masking in single-word
scenario in bootcount.c, which allowed clobbering of the magic half
when storing the value. With this change the clobbering preventing
behavior becomes consistent with existing single word bootcount storing
implementations in bootcount_at91.c and bootcount_davinci.c.
Finally, we enable the DM I2C bootcount driver to work also in single
word (4 byte) mode, in addition to the pre-existing half-word (2 byte)
mode. By default the driver still operates in half word mode as so far,
but can now be used alternatively in single word mode by adding
'size = <0x4>;' in the associated device tree node.
Link: https://lore.kernel.org/r/[email protected]
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In addition to pre-existing half-word (2 byte) mode, add support for
the driver to work also in single word (4 byte) mode by adding
'size = <0x4>;' in the device tree node.
Signed-off-by: Niko Mauno <[email protected]>
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When storing the single word bootcount value, apply the bootcount count
mask to prevent clobbering the magic half of the value.
Signed-off-by: Niko Mauno <[email protected]>
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Use predefined bit masks in operations where only the magic half or
only the count half of the 32-bit value are processed.
Signed-off-by: Niko Mauno <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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The MT798x series SoCs have IES regiter definitions. They should
belong to the pinctrl v1 revision.
Signed-off-by: Shiji Yang <[email protected]>
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Add support for MT8195 pinctrl. The driver is based on the kernel one.
Signed-off-by: Chris-QJ Chen <[email protected]>
Signed-off-by: Julien Stephan <[email protected]>
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Julien Stephan <[email protected]> says:
This series adds basic support for Mediatek soc MT8195:
- clock driver
- watchdog
- add a new macro helper to define gate clock. Other driver can be
cleaned later to use the new macro
Other driver will be added later.
It will also serve as basis for board support such as MT8395_EVK based
on MT8195.
Link: https://lore.kernel.org/r/[email protected]
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The following clocks have been added for MT8195 SoC:
apmixedsys, topckgen, infracfg
These clocks driver are based on the ones present in the kernel:
drivers/clk/mediatek/clk-mt8195-*
Signed-off-by: Chris-QJ Chen <[email protected]>
Signed-off-by: Julien Stephan <[email protected]>
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Add helper macro for mtk_gate, the same way, there are macros for
FIXED_CLK, MUX and FACTOR.
Signed-off-by: Julien Stephan <[email protected]>
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This adds basic support for MediaTek MT8195 SoC.
Add watchdog support by adding upstream compatible string.
Signed-off-by: Julien Stephan <[email protected]>
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Julien Stephan <[email protected]> says:
I recently submitted the clock driver for MT8188. I naively submitted a
driver that was ported from the kernel driver, and mostly work to boot a
kernel.
Recently David Lechner, added support for the clk dump command for
Mediatek clock drivers, so I used it to check the MT8188 and found
several issues fixed on this series:
- removed topckgen_cg, gates are now part of topckgen
- fixed several parents clocks
- added missing fixed clocks
While at it, I also refactored a bit the driver to improve readability,
and future additions to it.
Link: https://lore.kernel.org/r/[email protected]
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Refactor some part of the driver to improve readability and future
additions:
- use CLK_TOP_NR_CLK for added clocks
- rename the id map to make it more clear that the map applies to top
clocks only
- refactor the id map to improve readability
- xtal2_rate is only used for PLL clocks, so only the apmixedsys clock
tree needs it. Remove it elsewhere.
Signed-off-by: Julien Stephan <[email protected]>
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Fix a number of clock parent definitions for MT8188 clocks.
Signed-off-by: Julien Stephan <[email protected]>
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CLK_TOP_CLK13M was missing, add it.
Signed-off-by: Julien Stephan <[email protected]>
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FACTOR1(CLK_TOP_APLL1_D4, CLK_TOP_APLL1, 1, 3)
--> CLK_TOP_APLL1_D4 declares CLK_TOP_APLL1 as it's parents
MUX_GATE(CLK_TOP_APLL1, apll1_parents, 0x0F8, 0, 4, 7)
--> CLK_TOP_APLL1 declares apll1_parents as it's parents
static const int apll1_parents[] = {
CLK_TOP_CLK26M,
CLK_TOP_APLL1_D4
};
--> CLK_TOP_APLL1_D4 is a parent of CLK_TOP_APLL1
Fix this, by correctly setting CLK_TOP_APLL1_DX parent to CLK_APMIXED_APLLX
Signed-off-by: Julien Stephan <[email protected]>
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Remove the separate topckgen-cg driver for handling clock gates in the
topckgen address space.
Commit 8aeeeff50d46 ("clk: mediatek: allow gates in topckgen drivers")
added support for gates in topckgen driver.
This commit fixes MT8188 driver, the same way commit ba207d7f54f9 ("clk:
mediatek: mt8365: remove separate topckgen-cg driver") does for MT8365.
Signed-off-by: Julien Stephan <[email protected]>
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tooling"
Raymond Mao <[email protected]> says:
From: Raymond Mao <[email protected]>
This series finish the last missing puzzle of required SMBIOS types by:
1) Fixing duplicated handles when multiple instances exist in one type;
2) Implementing the rest of required types 9/16/17/19;
3) Adding version control when printing properties for all types.
Type 9/16/17/19 are generally DT-based, the idea is to write these tables
using a hybrid approach:
Explicit DT definitions under existing '/smbios/smbios' take precedence,
with fallback to scan and interpret values from the entire DT.
Moreover, all below APIs:
smbios_get_val_si()
smbios_get_u64_si()
smbios_add_prop_si()
are on top of sysinfo, thus allow vendors to get values from other
subsystems by implementing their own sysinfo driver if needed.
Link: https://lore.kernel.org/r/[email protected]
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This commit implements SMBIOS Type 16 (Physical Memory Array)
generation with a hybrid approach supporting both:
1. Explicit definition via Device Tree 'smbios' node:
Child node under '/smbios/smbios/memory-array' will be used to
populate as individual Type 16 structure directly.
- Properties follow SMBIOS field names with lowercase letters and
hyphen-separated words (e.g., 'memory-error-correction',
'maximum-capacity', 'extended-maximum-capacity', etc.).
- This method supports precise platform-defined overrides and system
descriptions.
2. Fallback to automatic DT-based discovery:
If child node under '/smbios/smbios/memory-array' does not exist,
the implementation will:
- Scan all top-level 'memory@' nodes to populate Type 16 structure with
inferred size and location data.
- Scan nodes named or marked as 'memory-controller' and parse
associated 'dimm@' subnodes (if present) to extract DIMM sizes and
map them accordingly.
This dual-mode support enables flexible firmware SMBIOS reporting while
aligning with spec-compliant naming and runtime-detected memory topology.
Type 16 support is under GENERATE_SMBIOS_TABLE_VERBOSE to avoid
increasing rom size for those platforms which only require basic SMBIOS
support.
Signed-off-by: Raymond Mao <[email protected]>
Tested-by: Ilias Apalodimas <[email protected]>
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Peng Fan (OSS) <[email protected]> says:
This patch set primarily removes unused DECLARE_GLOBAL_DATA_PTR
instances.
Many files declare DECLARE_GLOBAL_DATA_PTR and include
asm/global_data.h even though gd is never used. In these cases,
asm/global_data.h is effectively treated as a proxy header, which is
not a good practice.
Following the Include What You Use principle, files should include
only the headers they actually depend on, rather than relying on
global_data.h indirectly. This approach is also adopted in Linux kernel
[1].
The first few patches are prepartion to avoid building break after
remove the including of global_data.h.
A script is for filtering the files:
list=`find . -name "*.[ch]"`
for source in ${list}
do
result=`sed -n '/DECLARE_GLOBAL_DATA_PTR/p' ${source}`
if [ "${result}" == "DECLARE_GLOBAL_DATA_PTR;" ]; then
echo "Found in ${source}"
result=`sed -n '/\<gd\>/p' ${source}`
result2=`sed -n '/\<gd_/p' ${source}`
result3=`sed -n '/\<gd->/p' ${source}`
if [ "${result}" == "" ] && [ "${result2}" == "" ] && [ "${result3}" == "" ];then
echo "Cleanup ${source}"
sed -i '/DECLARE_GLOBAL_DATA_PTR/{N;/\n[[:space:]]*$/d;s/.*\n//;}' ${source}
sed -i '/DECLARE_GLOBAL_DATA_PTR/d' ${source}
sed -i '/global_data.h/d' ${source}
git add ${source}
fi
fi
done
[1] https://lpc.events/event/17/contributions/1620/attachments/1228/2520/Linux%20Kernel%20Header%20Optimization.pdf
CI: https://github.com/u-boot/u-boot/pull/865
Link: https://lore.kernel.org/r/[email protected]
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Remove DECLARE_GLOBAL_DATA_PTR from files where gd is not used, and
drop the unnecessary inclusion of asm/global_data.h.
Headers should be included directly by the files that need them,
rather than indirectly via global_data.h.
Reviewed-by: Patrice Chotard <[email protected]> #STMicroelectronics boards and STM32MP1 ram test driver
Tested-by: Anshul Dalal <[email protected]> #TI boards
Acked-by: Yao Zi <[email protected]> #TH1520
Signed-off-by: Peng Fan <[email protected]>
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struct fdt_resource, u32 and bool types are used in this header, add
missing header files following "include what you use".
Signed-off-by: Peng Fan <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-microblaze into next
AMD/Xilinx/FPGA changes for v2026.07-rc1
gpio:
- Add gpio delay driver
zynqmp:
- Wire gpio usb delay
- Enable SPL pinctrl per pin
xilinx:
- Enable NFS support
versal2:
- Extend DDR initialization
zynqmp-rtc:
- Use clock framework for calibration value
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https://source.denx.de/u-boot/custodians/u-boot-tpm into next
CI: https://source.denx.de/u-boot/custodians/u-boot-tpm/-/pipelines/29283
An update on AB subsystem allowing multiple FWU metadata
storage drivers to be selected simultaneously instead of
being mutually exclusive. The board can then select the
appropriate driver at runtime based on the devicetree
description.
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The cdns3_bind() function is responsible for identifying the appropriate
driver to bind to the USB Controller's device-tree node. If the device-tree
node has the 'dr_mode' property set to 'otg', the existing approach fails
to bind a driver, leading to loss of functionality.
To address this, use the VBUS Valid field of the OTG Status register to
determine the role as follows:
- If VBUS Valid field is set, it indicates that a USB Host is supplying
power and the Controller should assume the Peripheral role.
- If VBUS Valid field is clear, it indicates the absence of a USB Host and
the Controller should assume the Host role.
Additionally, when 'dr_mode' happens to be 'otg' and the STRAP settings
are not specified, use VBUS Valid to determine the role in cdns3_drd_init()
and assign it to cdns->dr_mode.
Signed-off-by: Siddharth Vadapalli <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-socfpga into next
This pull request updates SoCFPGA platforms with DDR improvements, new
board support, Agilex5 enhancements and general cleanup across the
codebase.
DDR and memory handling
* Add DRAM size checking support for Arria10.
* Widen MEM_TOTAL_CAPACITY mask handling in IOSSM mailbox driver.
* Assign unit address to memory node for improved memory
representation and consistency.
Agilex / Agilex5 updates
* Restore multi-DTB support for NAND boot and fix NAND clock handling.
* Enable SD card UHS mode and eMMC HS200/HS400 mode support on Agilex5.
* Fix DT property naming conventions for Agilex5.
* Exclude AGILEX_L4_SYS_FREE_CLK from clock enable/disable operations
to avoid unintended clock control.
New board support
* Add support for CoreCourse Cyclone V boards:
* AC501
* AC550
Including device trees, QTS configuration, defconfigs and maintainers
entries.
Fixes and cleanup
* Fix GEN5 handoff script path.
* Remove incorrect CONFIG_SPL_LDSCRIPT settings.
* Replace legacy TARGET namespace and perform related cleanup across
SoCFPGA code.
* General Kconfig, build and SoCFPGA maintenance updates.
Overall this pull request improves platform robustness, adds new board
coverage and cleans up legacy configuration usage across the SoCFPGA
U-Boot codebase.
[trini: Change TARGET_SOCFPGA_CYCLONE5 to ARCH_SOCFPGA_CYCLONE5 in the
new platforms this added]
Signed-off-by: Tom Rini <[email protected]>
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Add a test when delay is set to 0 to improve performances
by 20% on ARM based systems
Signed-off-by: Jean-Marie Verdun <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
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TARGET namespace is for machines / boards / what-have-you that
building U-Boot for. Simply replace from TARGET to ARCH
make things more clear and proper for ALL SoCFPGA.
Signed-off-by: Brian Sune <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
# Conflicts:
# drivers/ddr/altera/Makefile
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The previous mask for MEM_TOTAL_CAPACITY_INTF was limited to 8 bits,
which could truncate DDR size values on larger-memory systems.
Update INTF_CAPACITY_GBITS_MASK to 32 bits to correctly represent
the full capacity field according to the hardware specification.
Signed-off-by: Naresh Kumar Ravulapalli <[email protected]>
Signed-off-by: Chen Huei Lok <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]> Best regards,
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operations
AGILEX_L4_SYS_FREE_CLK is a free-running clock with no gate control in
hardware, therefore attempting to enable or disable it is not applicable.
Update the clock driver to explicitly exclude this clock ID from
enable/disable operations by returning -EOPNOTSUPP in bitmask_from_clk_id()
and treating this as a no-op in the socfpga_clk_enable() and
socfpga_clk_disable() functions.
This prevents unnecessary register access for clocks that cannot be gated
and ensures clean handling when the clock is present in the device tree.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Add DRAM size checking compare between size from device tree and actual
hardware.
Trigger hang if DRAM size from device tree is greater than actual hardware.
Display warning message if DRAM size mismatch between device tree and
actual hardware.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]> Best regards,
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In v2025.10, the Agilex clock driver was updated to support
clk_enable() and clk_disable() using clock-ID based bitmasks.
However, only AGILEX_NAND_CLK was implemented, while the NAND DT
node still referenced both nand and nand_x clocks.
Since AGILEX_NAND_X_CLK is not defined in the clock driver or the
clock-ID specification, clk_enable() failed during NAND probe.
As a result, the Denali NAND controller never completed
initialization.
Fix this by mapping the NAND X clock to the existing l4_mp clock
bitmask, aligning the DT expectations with the clock driver and
restoring proper NAND controller initialization.
Signed-off-by: Dinesh Maniyam <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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In theory, for the same vendor, we should use the same instructions as
the spi-nor-core implementation.
Fixes: 72151ad10f8d ("mtd: spi-nor-core: Add Cypress manufacturer ID in set_4byte")
Fixes: 5bf3f3dd11db ("mtd: spi-nor: Enable QE bit for ISSI flash")
Signed-off-by: Shiji Yang <[email protected]>
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These chips are internally made of two/four dies with linear addressing
capabilities to make it transparent to the user that two/four dies were
used. There is one drawback however, the read status operation is racy
as the status bit only gives the active die status and not the status of
the other die. For commands affecting the two dies, it means if another
command is sent too fast after the first die has returned a valid
status (deviation can be up to 200us), the chip will get corrupted/in an
unstable state.
The solution adopted here is to iterate manually over all internal
dies (which takes about 30us per die) until all are ready. This approach
will always be faster than a blind delay which represents the maximum
deviation, while also being totally safe.
A flash-specific hook for the status register read had to be
implemented. Testing with the flash_speed benchmark in Linux shown no
difference with the existing performances (using the regular status read
core function).
As the presence of multiple dies is not filled in these chips SFDP
tables (the table containing the crucial information is optional), we
need to manually wire the hook.
This change is adapted from Linux.
Link: https://lore.kernel.org/all/20250110-winbond-6-12-rc1-nor-volatile-bit-v3-1-735363f8cc7d@bootlin.com/
Signed-off-by: Miquel Raynal <[email protected]>
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Invert the conditional when to exit, and fall back to common code
in the default case. This should have no functional impact on either
code path.
Signed-off-by: Marek Vasut <[email protected]>
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The spi_slave_of_to_plat() is called from one place, spi_child_post_bind().
Squash it into the later and remove the public declaration, make this
function local static. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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Some Winbond Flash chips share the same device ID. Names are not that
important for the SPI Flash, hence we don't need these duplicate ID
definitions. And the Flash size of w25q512jv is actually wrong. Clean
them up to keep the source file tidy.
Signed-off-by: Shiji Yang <[email protected]>
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Change the Kconfig from a "choice" to a conditional block, allowing
multiple FWU metadata storage drivers to be selected simultaneously
instead of being mutually exclusive.
This enables systems with FWU metadata on different storage types
(e.g., both GPT-partitioned block devices and MTD devices) to have
both drivers compiled in. The board can then select the appropriate
driver at runtime based on the devicetree description.
The change converts FWU_MDATA to a menuconfig and replaces the
"choice/endchoice" block with "if FWU_MDATA/endif", making
FWU_MDATA_GPT_BLK default to 'y' for backward compatibility.
Signed-off-by: Kory Maincent <[email protected]>
Acked-by: Sughosh Ganu <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Ilias Apalodimas <[email protected]>
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Add a GPIO controller driver that provides configurable delays when
setting GPIO output values. This is useful for hardware that requires
specific timing delays during power sequencing or GPIO state changes.
The driver wraps underlying GPIO controllers and adds programmable
ramp-up and ramp-down delays specified in microseconds through the
device tree. Each GPIO can have independent delay timings.
Device tree binding matches Linux.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/575998efc6ba0e405640789cf8d05f0b633f496e.1770105146.git.michal.simek@amd.com
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Although the pinctrl pm requests are implemented in the PMU firmware,
PM_QUERY_DATA is actually implemented in ATF. In SPL (or when running in
EL3), ATF is not yet running, so we need to implement this API
ourselves. Do the bare minimum, allowing SPL to enumerate functions, but
don't bother with groups. Groups take up a lot of space, and can be
emulated with pins. For example, a node like
display-port {
mux {
groups = "dpaux0_1";
function = "dpaux0";
};
};
can be replaced by
display-port {
mux {
pins = "MIO34", "MIO35", "MIO36", "MIO37";
function = "dpaux0";
};
};
While this isn't backwards-compatible with existing devicetrees, it's
more than enough for SPL where we may only need to mux one or two pins.
Add SPL_PINCTRL_ZYNQMP to ensure there's no SPL size growth when pinctrl
is enabled in U-Boot but isn't necessary for SPL. The only config this
would affect is Kria, but SPL_PINCTRL_GENERIC is disabled so
SPL_PINCTRL_ZYNQMP is not selected.
Signed-off-by: Sean Anderson <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Add support for reading RTC clock from device tree using clock
framework also update the default calibration value to 0x7FFF
as per RTC specifications.
Falls back to 'calibration' property if clock unavailable, and uses
default calibration if neither is present. Only writes calibration when
hardware register reads zero.
The calibration write previously in zynqmp_rtc_set() has been moved to
the probe function. The earlier implementation wrote calibration on
every time update to clear the tick counter, but since calibration is
now dynamically configured from clock framework or device tree during probe,
it only requires one-time initialization. This avoids repeated tick
counter resets and unnecessary overhead.
Signed-off-by: Pranav Tilak <[email protected]>
Reviewed-by: Tomas Melin <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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https://source.denx.de/u-boot/custodians/u-boot-microblaze
AMD/Xilinx/FPGA changes for v2026.04-rc3
clk:
- zynqmp clk fixes
phy:
- sync vsc8541 config
versal2:
- fix GIC configuration
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https://source.denx.de/u-boot/custodians/u-boot-dfu
u-boot-dfu-20260211
USB Gadget:
* dwc3: Support ip and version type
* dwc3: Increase controller halt timeout
* dwc3: Don't send unintended link state change
* dwc3: Improve reset sequence
* dwc2: Move dr_mode check to bind to support RK3288/RK3506 with
2 DWC2 controllers
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