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Linux uses get_modes() to fetch all available panel modes from the
driver. This is also used to fetch the modes from Linux's simple panel
implementation where a list of drm_display_mode structs is used to
define the different possible panels.
To make our work easier, create a compatible way of fetching and
defining these modes in u-boot. get_modes() fetches the available modes
from the panel driver. The get_display_timing() call maps the
drm_display_mode properties to the display_timing struct. This call now
uses whatever panel operation is available, get_display_timing() or
get_modes().
Reviewed-by: Fabio Estevam <[email protected]>
Signed-off-by: Markus Schneider-Pargmann (TI.com) <[email protected]>
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The Linux support for dwc3 on Apple silicon SoCs switched to using a
apple specific glue driver [1] that uses it own compatible string. The
glue driver handles platform specific requirements on the interaction
between dwc3 and the USB2/USB3 PHY and reset-controller for USB role
switches and plug events.
To keep USB working as before when the nodes still carried "snps,dwc3"
as compatible add "apple,t8103-dwc3" to the of match table. Eventually
it is probably advisable to add a dwc3-apple glue driver and write code
for the currently empty Apple Type-C PHY driver in phy-apple-atc.c.
Link: https://lore.kernel.org/asahi/[email protected]/ [1]
Reviewed-by: Neal Gompa <[email protected]>
Reviewed-by: Mark Kettenis <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Signed-off-by: Janne Grunau <[email protected]>
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The micrel KSZ9031 phy has a optional clock pin (CLK125_NDO) which can be
used as reference clock for the MAC unit. The clock signal must meet the
RGMII requirements to ensure the correct data transmission between the
MAC and the PHY. The KSZ9031 phy does not fulfill the duty cycle
requirement if the phy is configured as slave. For a complete
describtion look at the errata sheets: DS80000691D or DS80000692D.
The errata sheet recommends to force the phy into master mode whenever
there is a 1000Base-T link-up as work around. Only set the
"micrel,force-master" property if you use the phy reference clock provided
by CLK125_NDO pin as MAC reference clock in your application.
Attention: this workaround is only usable if the link partner can
be configured to slave mode for 1000Base-T.
This follows linux implementation in commit
e1b505a60366 ("net: phy: micrel: add 125MHz reference clock workaround")
Signed-off-by: Markus Niebel <[email protected]>
Signed-off-by: Max Merchel <[email protected]>
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Disable the support due to chip errata and call genphy_config_aneg
instead of genphy_config. For a complete describtion look at the
KSZ9031 errata sheets: DS80000691D or DS80000692D.
Micrel KSZ9021 has no errata, but has the same issue with Asymmetric Pause.
This patch apply the same workaround as the one for KSZ9031.
This follows linux implementation in commits
3aed3e2a143c ("net: phy: micrel: add Asym Pause workaround")
407d8098cb1a ("net: phy: micrel: add Asym Pause workaround for KSZ9021")
Signed-off-by: Markus Niebel <[email protected]>
Signed-off-by: Max Merchel <[email protected]>
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Replace PHY interface mode bitmap handling with comparison test to match
U-Boot PHY subsystem behavior. U-Boot currently implements only single PHY
interface mode for each PHY. Linux currently uses bitmap of PHY interface
modes for each PHY.
The reason why in Linux uses bitmap of supported interface modes is so
that Linux can select the best serdes mode switching behavior for the PHY.
For example if the host only supports 10gbase-r serdes mode, then the PHY
must always talk to the host in 10gbase-r mode, even if the RJ-45 copper
speed was autonegotiated to lower speed (i.e. 1Gbps).
If the host supports both 10gbase-r and sgmii serdes modes, we want the
PHY to switch to sgmii if the RJ-45 speed is 1000/100/10, and to switch
to 10gbase-r if the RJ-45 speed is 10000.
U-Boot does not implement this functionality yet, therefore remove modes
which cannot be currently supported and switch mv_test_bit() to plain
mode comparison.
Fixes: b6fcab0728cb ("net: phy: marvell10g: Adapt Marvell 10G PHY driver from Linux")
Signed-off-by: Marek Vasut <[email protected]>
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Add Microsemi/Microchip MDIO driver for interfaces found in their network
switches.
Driver is based on the Linux version.
Signed-off-by: Robert Marko <[email protected]>
Acked-by: Jerome Forissier <[email protected]>
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A lot of things can go wrong while parsing dfu_alt_info. Make sure to
pass the real error codes all the way up instead of replacing them with
an unhelpful -1.
Signed-off-by: Sean Anderson <[email protected]>
Reviewed-by: Mattijs Korpershoek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mattijs Korpershoek <[email protected]>
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Correct USB30 primary clock RCG configuration and add missing
USB3_PRIM_PHY_AUX_CMD_RCGR RCG configuration.
Above taken from Linux commit 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p")
Add missing USB3_PRIM_PHY_PIPE_CLK gate clock definition.
Extend reset map with USB-related BCR entries and video BCR
for comprehensive reset control support.
Signed-off-by: Balaji Selvanathan <[email protected]>
Link: https://patch.msgid.link/[email protected]
[casey: indentation fix]
Signed-off-by: Casey Connolly <[email protected]>
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Add clock gate definitions and entries for QUP (Qualcomm Universal
Peripheral) serial engine clocks across all four wrappers on SA8775P.
This enables proper clock management for I2C, SPI, and UART
peripherals connected to the QUP blocks.
This resolves the "unknown clock ID 133" error for UART10 and
provides complete QUP clock infrastructure for the platform.
Signed-off-by: Swathi Tamilselvan <[email protected]>
Signed-off-by: Balaji Selvanathan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Currently we don't properly map between the regulator mode ID enum and
the appropriate register values in the mode map, as a result we always
unintentionally vote for retention mode if we actually attempt to set
it. In the set_mode path we did find the appropriate entry in the mode
map but we wrote the id instead of the register values. Clean this up
and properly map id -> mode and vice versa.
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Make use of the new RPMh read support to fetch regulator values that may
have been voted on by a previous bootloader stage. This allows commands
like "regulator status" to report the actual votes programmed into
hardware (though not necessarily the actual states of the regulators
once the votes have been aggregated).
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Implement support for RPMh reads, these allow reading out the
current votes for RPMh controlled resources such as regulators and
interconnects.
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Several bugs were discovered in the rpmh-rsc driver which collectively
meant we were never actually waiting for the TCS to flush, these were
likely missed because U-Boot runs single threaded and the RPMh had
typically processed the single command we sent by the time we went
to send the next one. However a future patch will implement rpmh read
support which requires us to properly wait for the RPMh command response
so we can return the value.
Fix these issues so we correctly ensure the TCS is done before
returning.
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Add some comments explaining a few of the RSC registers
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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If we don't reclaim and clear the IRQ bits, we might get a spurious
interrupt from this TCS in Linux:
WARNING: CPU: 0 PID: 0 at drivers/soc/qcom/rpmh-rsc.c:451 tcs_tx_done+0x98/0x270
...
Call trace:
tcs_tx_done+0x98/0x270 (P)
__handle_irq_event_percpu+0x60/0x220
handle_irq_event+0x54/0xc0
handle_fasteoi_irq+0xa8/0x1c0
handle_irq_desc+0x3c/0x68
generic_handle_domain_irq+0x24/0x40
gic_handle_irq+0x5c/0xd0
...
Signed-off-by: Neil Armstrong <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Failing to enable clocks will lead to bus hangs and the board crashing
in some cases, let's actually deal with this error and fail probe rather than hoping the clocks are already enabled.
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Add more clocks for UART2, i2c9 and a few others. This is enough to get
the rubikpi 3 working.
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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PMIC Arbiter may expose multiple owned and non-owned APIDs per SID/PID.
- Keep current mapping if it is OWNED and a NON-OWNED appears.
- Always update when a NEW OWNED APID appears (make writable).
- If current is NON-OWNED and a new NON-OWNED appears, update to it
(remain read-only).
This avoids write-access violations when not using the newly discovered
owned channels.
Signed-off-by: Aswin Murugan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Introduce an SDHCI ops hook (config_dll) for MSM SDHCI and implement a
minimal DLL control routine that ensures the core DLL is disabled when
the bus clock is at or below 100 MHz. This approach mirrors the Linux
MSM SDHCI driver.
Signed-off-by: Sumit Garg <[email protected]>
Signed-off-by: Loic Poulain <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Add support for configuring the SDCC1 apps clock on QCM2290 by introducing
a frequency table and enabling dynamic rate setting. Previously, the clock
was assumed to be fixed at 384 MHz by firmware, which limited flexibility
and correctness when selecting optimal rates for SD/MMC operations.
Suggested-by: Sumit Garg <[email protected]>
Signed-off-by: Loic Poulain <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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When 'max-clk' is not specified, the SDHCI core retrieves the base clock
from the SDHCI_CAPABILITIES register (bits [15:8]). However, this field
is unreliable on MSM SDHCI controllers, as noted by the Linux driver
using the SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN flag. In addition, the field
is only 8 bits wide and cannot represent base clocks above 255 MHz.
On platforms like Agatti/QCM2290, the firmware sets the SDHCI clock to
384 MHz, but the capabilities register reports 200 MHz. As a result,
the core calculates a divider of 4, producing a 96 MHz SDCLK instead of
the intended ~52 MHz. This overclocking can cause sporadic CRC errors
with certain eMMC.
To fix this, use the actual clock rate reported by the SDHCI core clock
instead of relying on the capabilities register for divider calculation.
Signed-off-by: Loic Poulain <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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This change is imported from Linux driver and tested with SM6125 SoC.
Note, the msm8996_phy_cfg struct is same as sdm660_phy_cfg but
qusb2_phy_cfg::se_clk_scheme_default differs only.
Signed-off-by: Biswapriyo Nath <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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The power on function for the phy only deasserts the reset, so the phy
might be in a weird state that we don't clean up properly.
Assert the reset in probe() so that when we power on we will have the
phy in a clean state.
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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host count
The SMEM driver was failing to resolve memory regions on some boards
because `dev_of_offset()` + `fdtdec_lookup_phandle()` did not yield a
valid DT node. Modernize the code to use driver-model/ofnode accessors
and make the probe robust for both DT styles (direct `reg` vs
`memory-region` phandle).
- qcom_smem_map_memory():
* Drop fdtdec path; use dev_read_phandle_with_args() +
ofnode_read_resource().
* Use dev_read_phandle_with_args() +
fnode_read_resource().
- qcom_smem_probe():
* Try dev_read_addr_size() first (map via <reg>), else fall back to
qcom_smem_map_memory() with "memory-region".
* Check "qcom,rpm-msg-ram" presence to add second region.
- Additionally, SMEM_HOST_COUNT is increased to support newer SMEM
versions that include more remote processors. This avoids failures
during processor ID checks.
Signed-off-by: Aswin Murugan <[email protected]>
Reviewed-by: Varadarajan Narayanan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Introduce a new Kconfig option PINCTRL_QCOM_GENERIC that, when selected,
enables all Qualcomm pinctrl drivers by default. This simplifies defconfigs
for platforms supporting multiple SoCs and avoids manual driver selection.
Individual drivers can still be disabled if required.
Signed-off-by: Aswin Murugan <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Add pinctrl driver for QCS615. Driver code is based on the
similar U-Boot and Linux drivers.
Signed-off-by: Aswin Murugan <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Add the PM8150, PM8350, and PM7325 regulator data found on Qualcomm
platforms. These regulator tables are imported from the Linux driver
to enable support for these PMICs in U-Boot.
Signed-off-by: Aswin Murugan <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Correct ARCH_QCOM to ARCH_SNAPDRAGON as ARCH_QCOM is outdated/unused
config. Using ARCH_QCOM was causing USB fastboot mode to fail.
Signed-off-by: Balaji Selvanathan <[email protected]>
Reviewed-by: Mattijs Korpershoek <[email protected]>
Acked-by: Mattijs Korpershoek <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Added delays before and after setting the PIPE_UTMI_CLK_SEL and
PIPE3_PHYSTATUS_SW bits in the Qscratch GENERAL_CFG register
during UTMI clock selection for DWC3 on Qualcomm platforms.
These delays help ensure proper timing and stability of the UTMI
clock switching sequence, potentially avoiding race conditions or
unstable PHY behavior during initialization.
Tested on platforms using Qscratch-based DWC3 PHY configuration.
This change is taken from this Linux kernel implementation:
https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/usb/dwc3/dwc3-qcom.c?id=a4333c3a6ba9ca9cff50a3c1d1bf193dc5489e1c
Signed-off-by: Balaji Selvanathan <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Mattijs Korpershoek <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Added a check to ensure the requested timeout does not exceed the
hardware's maximum supported value. This prevents register overflow
and ensures watchdog reliability.
So, added a check in qcom_wdt_start() to ensure the requested timeout
does not exceed the hardware-supported maximum value. If the requested
value exceeds the maximum value, then the timeout is clamped
at maximum value.
The timeout is first converted to watchdog ticks and then compared
against QCOM_WDT_MAX_TIMEOUT. This helps prevent misconfiguration
and potential watchdog misbehavior due to overflow.
QCOM_WDT_MAX_TIMEOUT is set to 0xFFFFF, as Qualcomm SoCs typically
use 20 bits to store bark/bite timeout values.
This work builds upon the previous submission:
https://lore.kernel.org/u-boot/[email protected]/
Signed-off-by: Gopinath Sekar <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Ported from the Mediatek SDK. The upstream Linux kernel also has the
same register map as the SDK.
Signed-off-by: Shiji Yang <[email protected]>
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The "fixed-layout" nvmem controller subnode used to be optional wrapper
around nvmem controller cells subnodes. The "fixed-layout" node is now
mandatory in most cases, but in order to support both recent and legacy
DTs, both variants have to be supported.
Implement support for the "fixed-layout" node in the most trivial manner,
check whether the nvmem cell supernode is compatible with "fixed-layout"
and if it is, proceed one level above it to find the nvmem controller.
Signed-off-by: Marek Vasut <[email protected]>
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David Lechner <[email protected]> says:
MT8365 has different pinctrl register layout compared to other SoCs in
the family, so needs its own driver.
This is also the first SoC in this family supported in U-Boot using an
upstream devicetree that has the mediatek,pctl-regmap property, so we
need to add support for that to the common mediatek pinctrl code first.
Link: https://lore.kernel.org/r/[email protected]
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Add pinctrl support for MT8365 SoC.
Signed-off-by: Julien Masson <[email protected]>
Signed-off-by: Vitor Sato Eschholz <[email protected]>
Signed-off-by: David Lechner <[email protected]>
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Add support for the mediatek,pctl-regmap devicetree property to the
common MediaTek pinctrl driver.
In upstream devicetrees from Linux, the pinctrl nodes may be on the
interrupt controller register address space rather than the pinctrl
register address space. In this case, there is a syscon node linking to
the actual pinctrl registers. This uses a common property name of
mediatek,pctl-regmap for the phandle to the syscon node.
The logic here is that if this property is present, we look up the
syscon node and use it's address as the base address of the pinctrl
registers and ignore the pinctrl node's own reg property. (Support
for interrupts could be added later if needed.)
There is also at least one SoC in Linux that has two syscon phandles
in this property. This implementation support parsing this, but doesn't
do anything with the second syscon yet (the 2nd syscon is for interrupts
which we are saving for later).
Signed-off-by: David Lechner <[email protected]>
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Use a ID map to add clocks for the missing CLK_TOP_CLK32K and
CLK_TOP_CLK26M that were not included in the devicetree definitions.
This fixes getting the rate of any clock that had one of these as a
parent.
CLK_TOP_UNIVPLL does not appear to be a real clock, so it is omitted
now since we can do that with the ID map as well.
Signed-off-by: David Lechner <[email protected]>
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Remove the separate topckgen-cg driver for handling clock gates in the
topckgen address space. The devicetree bindings for this were not
acceptable upstream because it was creating a separate clock controller
using the same address space as the main topckgen clock controller. The
gates are moved to the topckgen tree instead.
Signed-off-by: David Lechner <[email protected]>
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Add handling for gates in the topckgen clk drivers. This avoids the need
to have separate topckgen-cg drivers and devicetree nodes for the same
address space and clock ID range.
Signed-off-by: David Lechner <[email protected]>
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Split the struct mtk_clk_tree for MT8365 into separate structures for
the apmixedsys, topckgen and infracfg clock controllers. This is needed
to support moving the topckgen gates into the struct mtk_clk_tree. Since
apmixedsys can also have gates, we need separate structures.
Signed-off-by: David Lechner <[email protected]>
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Fix a number of clock parent definitions for MT8365 clocks. Most of
these are just informational or don't make a function change.
The clocks with the new PLL_FACTOR2 macro and the change in apu_parents
are fixing actual bugs.
Signed-off-by: David Lechner <[email protected]>
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Add a flags field to struct mtk_fixed_clk to allow properly resolving
the parent clock. All chip-specific clocks are updated to populate this
field correctly.
The parent is currently only used for printing debug information, so
there are no functional bugs being fixed.
Signed-off-by: David Lechner <[email protected]>
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Add a gates_offs field to struct mtk_cg_priv and use that instead of
struct mtk_clk_tree.gates_offs.
Prior to this change, struct mtk_clk_tree.gates_offs could be the offset
of struct mtk_clk_tree.gates or struct mtk_cg_priv.gates depending on
the context. This was confusing and error-prone. For example, in mt8365
there is one set of gates that needs an offset and one that does not
that share the same struct mtk_clk_tree. This is fixed in this patch by
giving the correct offset for each gate separately.
Signed-off-by: David Lechner <[email protected]>
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Fix a few missing clocks and even more clocks in the incorrect order.
Since the clocks are looked up by index, having them out of order or
skipping an ID will lead to incorrect clocks being used.
Signed-off-by: David Lechner <[email protected]>
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David Lechner <[email protected]> says:
I started looking into fixing some bugs in the mt8365 clock driver and
realized that there was no way to inspect or debug the clock trees.
I set out to implement the dump function to help with this. The driver
architecture didn't make this easy since there was no way to know the
number of elements in each of the clock arrays. The first few patches
in this series are adding fields to the data structures to hold this
information.
Once that was fixed, I was still getting crashes due to other bugs. To
work around this, I implemented the of_xlate function to validate clk
IDs as early as possible and return errors instead of crashing when
requested IDs are invalid. This also makes use of the new size fields
to prevent out of bounds array accesses. There are a couple of drivers
that remap IDs, so there are a few extra patches to handle that as well.
Then finally, I was able to implement the dump function to print out the
clock tree information without crashing. In the v1 cover letter, there
is an example of the output (it is quite long and doesn't need to be
repeated here).
Link: https://lore.kernel.org/r/[email protected]
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Implement dump callbacks for Mediatek clocks. On these platforms, there
are 100s of clocks, so it can be easy to miss mistakes. The dump
callbacks will be useful for debugging and verifying clock configs.
Signed-off-by: David Lechner <[email protected]>
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Add range initializers to the id_offs_map arrays in the mt7623 clk
driver to set unmapped IDs to -1. This prevents accidental usage of
unmapped IDs that would otherwise map to 0.
mtk_common_clk_of_xlate() checks these values for < 0 and returns
-ENOENT in that case.
A range initializer covering the entire array is used since it is less
error-prone than manually looking up the value of each macro in the
existing initializers and checking for gaps. It is placed first so that
the specific initializers override it.
Signed-off-by: David Lechner <[email protected]>
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Update documentation comments to clarify the difference between which
.id fields are mapped (only struct clk.id) vs. unmapped (all struct
mtk_*.id and .parent fields). The unmapped IDs are the ones defined
in the devicetree bindings, while the mapped IDs are the ones used as
the index into the various clk arrays.
Also fix spelling of "parent" while we are touching this.
Signed-off-by: David Lechner <[email protected]>
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Add driver-specific of_xlate ops for MediaTek clocks. This provides
better checking of the args passed from the devicetree. Compared to
the default of_xlate implementation, this will return -EINVAL if there
are zero args (id is always required) and -ENOENT if the id is out of
range for the clock type. This will protect against out of bounds array
accesses later on when the clk->id is used to index into the clock
data arrays.
If there is a id_offs_map, then we have to do that translation first
before checking the id to see if it is in range. There is no sense in
doing the mapping multiple times, so we save the mapped ID in clk->id
and remove mtk_clk_get_id().
mtk_clk_find_parent_rate() also had to be updated since it creates a
temporary struct clk to represent the parent clock. It now has do the
translation in case the parent clock also uses an id_offs_map.
Signed-off-by: David Lechner <[email protected]>
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Move all infrasys ops and related functions next to each other in the
file for better organization.
Generally all ops functions are grouped together like this for the other
ops types (apmixedsys, topckgen, etc). However the infrasys functions
were mixed in with the other sections making them harder to find. This
will also give a logical place to add any future infrasys-specific
functions.
Signed-off-by: David Lechner <[email protected]>
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Add id_offs_map_size field to struct mtk_clk_tree and populate it for
all existing drivers.
Currently, there is no bounds checking when accessing the id_offs_map
array. Adding this field will allow for bounds checking in the future.
Signed-off-by: David Lechner <[email protected]>
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