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This converts the following to Kconfig:
CONFIG_SCSI_AHCI_PLAT
CONFIG_SYS_SCSI_MAX_SCSI_ID
CONFIG_SYS_SCSI_MAX_LUN
CONFIG_SYS_SATA_MAX_DEVICE
Drop CONFIG_SCSI for everything except the sandbox build. We only need
one build for tests.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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This is defined based on two other CONFIGs for all boards except sandbox
and durian.
For sandbox the value does not matter. For durian the value seems
excessive.
Drop the option completely, to simplify configuration and reduce the
number of things we need to convert to Kconfig.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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At present all ahci drivers depend on AHCI except for DWC_AHCI. But no
boards enable that without also enabling AHCI:
/tools/moveconfig.py -f ~AHCI DWC_AHCI
0 matches
Group them together and sort them in order by Kconfig name (except for
AHCI_MVEBU which uses a different naming convention).
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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No boards use this driver without CONFIG_BLK, so clean up the dead code.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Move the SATA options inside an 'if SATA' part, so they are grouped.
Fix the 'Complient' typo while we are here.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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No boards currently use SATA without BLK:
./tools/moveconfig.py -f SATA ~BLK
0 matches
Make SATA depend on BLK to avoid any future confusion. Drop the dead code.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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This is not used in U-Boot and has not been converted to driver model.
Drop it.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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This converts the following to Kconfig:
CONFIG_SYS_IDE_MAXBUS
CONFIG_SYS_IDE_MAXDEVICE
CONFIG_SYS_ATA_BASE_ADDR
CONFIG_SYS_ATA_STRIDE
CONFIG_SYS_ATA_DATA_OFFSET
CONFIG_SYS_ATA_REG_OFFSET
CONFIG_SYS_ATA_ALT_OFFSET
CONFIG_SYS_ATA_IDE0_OFFSET
CONFIG_SYS_ATA_IDE1_OFFSET
CONFIG_ATAPI
CONFIG_IDE_RESET
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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This is not used in U-Boot anymore. Drop it.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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At present the IS_ENABLED() macro has extra brackets, making it possible
to write:
if IS_ENABLED(CONFIG_XXX)
but it is a bit confusing. Add the missing brackets.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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Seems that we need the waterlevel setting not only for PIO mode as
without this at least the i.MX 8M Mini won't boot anymore when being
written by such a U-Boot. Corruption has also been observed both on
the i.MX 6 as well as i.MX 8M Mini when using ums on the eMMC. Fix
this by setting the watermark level again regardless of whether in
DMA or PIO mode.
Fixes: 41c6a22fc296 ("mmc: fsl_esdhc_imx: simplify esdhc_setup_data()")
Signed-off-by: Marcel Ziswiler <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Tested-by: Fabio Estevam <[email protected]>
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In some cases, a single SerDes instance can be shared between two different
processors, each using a separate link. In these cases, the SerDes
configuration is done in an earlier boot stage. Therefore, add support to
skip reconfiguring, if it is was already configured beforehand.
Signed-off-by: Aswath Govindraju <[email protected]>
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Add register sequences for PCIe + QSGMII PHY multilink configuration.
Signed-off-by: Swapnil Jakhade <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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Add support for multilink configuration of Sierra PHY. Currently,
maximum two links are supported.
Signed-off-by: Swapnil Jakhade <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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Add single link PCIe register configurations for no SSC and internal
SSC. Also, add missing PMA lane registers for external SSC.
Signed-off-by: Swapnil Jakhade <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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PIPE phy status is used to communicate the completion of several PHY
functions. Check if PHY is ready for operation while configured for
PIPE mode during startup.
Signed-off-by: Swapnil Jakhade <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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Check if PMA cmn_ready is set indicating the startup process is complete.
Signed-off-by: Swapnil Jakhade <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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Add PHY PCS common register configuration sequences for single link.
Update single link PCIe register sequence accordingly.
Signed-off-by: Swapnil Jakhade <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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documentation
No functional change. Rename some regmap variables as mentioned in Sierra
register description documentation.
Signed-off-by: Swapnil Jakhade <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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Add support to get SSC type from DT.
Signed-off-by: Swapnil Jakhade <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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Sierra driver currently supports single link configurations only. Prepare
driver to support multilink multiprotocol configurations along with
different SSC modes.
Signed-off-by: Swapnil Jakhade <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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Fix the condition for setting P_ENABLE_FORCE bit, by syncing with the
driver in kernel.
Signed-off-by: Aswath Govindraju <[email protected]>
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Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has
two inputs, plllc_refclk (input from pll0_refclk) and refrcv (input from
pll1_refclk). Model PLL_CMNLC and PLL_CMNLC1 as a clock so that it's
possible to select one of these two inputs from device tree.
Signed-off-by: Aswath Govindraju <[email protected]>
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Add a driver of type UCLASS_PHY for each of the link nodes in the serdes
instance.
Signed-off-by: Aswath Govindraju <[email protected]>
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Add missing clk_disable_unprepare() in cdns_sierra_phy_remove().
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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Instead of having separate structure members for each input clock, add
an array for the input clocks within "struct cdns_sierra_phy". This is
in preparation for adding more input clocks required for supporting
additional clock combination.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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No functional change. Group devm_reset_control_get() and
devm_reset_control_get_optional() to a separate function.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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No functional change. Group all devm_clk_get_optional() to a
separate function.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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Cadence Sierra PHY driver registers PHY using devm_phy_create()
for all sub-nodes of Sierra device tree node. However Sierra device
tree node can have sub-nodes for the various clocks in addtion to the
PHY. Use devm_phy_create() only for nodes with name "phy" (or "link"
for old device tree) which represent the actual PHY.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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Commit 39b823381d9d ("phy: cadence: Add driver for Sierra PHY")
de-asserts PHY_RESET even before the configurations are loaded in
phy_init(). However PHY_RESET should be de-asserted only after
all the configurations has been initialized, instead of de-asserting
in probe. Fix it here.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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Updated values of USB3 related Sierra PHY registers.
This change fixes USB3 device disconnect issue observed
while enternig U1/U2 state.
Signed-off-by: Sanket Parmar <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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The driver enables IPU support. Basically enables the clocks,
timers, watchdog timers and bare minimal MMU and supports
loading the firmware from mmc.
Signed-off-by: Keerthy <[email protected]>
[Amjad: fix compile warnings]
Signed-off-by: Amjad Ouled-Ameur <[email protected]>
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Add remoteproc resource handling helpers. These functions
are primarily to parse the resource table and to handle
different types of resources. Carveout, devmem, trace &
vring resources are handled.
Signed-off-by: Keerthy <[email protected]>
[Amjad: fix redefinition of "struct resource_table" and compile warnings ]
Signed-off-by: Amjad Ouled-Ameur <[email protected]>
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Enable fs_loader compilation at SPL Level.
Signed-off-by: Keerthy <[email protected]>
[Amjad: fix compilation failures for J721e platform]
Signed-off-by: Amjad Ouled-Ameur <[email protected]>
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Add a reset driver to bring IPs out of reset.
Signed-off-by: Keerthy <[email protected]>
[Amjad: reset_ops structure member "free" has been renamed to "rfree",
use the latter instead]
Signed-off-by: Amjad Ouled-Ameur <[email protected]>
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There is a 4 bit VARIANT number inside the JTAGID register that TI
increments any time a new variant for a chip is produced. Each
family of TI's SoCs uses a different versioning scheme based off
that VARIANT number.
CC: Dave Gerlach <[email protected]>
Signed-off-by: Bryan Brattlof <[email protected]>
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Add support for J721S2 SoC identification.
Signed-off-by: David Huang <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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Add support for DDR subsystem in J721S2 SoC.
Signed-off-by: David Huang <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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Add support for J721S2 SoC.
Signed-off-by: David Huang <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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Add support for J721S2 SoC.
Signed-off-by: David Huang <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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Add support for DMA in J721S2 SoC.
Signed-off-by: David Huang <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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Multiple DDR subsystems
In Multi DDR subystems with interleaving support, the following needs to
configured,
- interleaving granular size and region
- EMIFs to be enabled
- EMIFs with ecc to be enabled
- EMIF separated or interleaved
- number of cycles of unsuccessful EMIF arbitration to wait before
arbitrating for a different EMIF port, by default set to 3
Add support for configuring all the above by using a MSMC device
Signed-off-by: Aswath Govindraju <[email protected]>
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The current driver only supports single instance of DRR subsystem. Add
support for probing multiple instances of DDR subsystem.
Signed-off-by: Aswath Govindraju <[email protected]>
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Add a pointer to ddr instance int the lpddr4_privatedata_s structure for
supporting mutliple instances of DDR in the drivers.
Signed-off-by: Aswath Govindraju <[email protected]>
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If there is an optional boot notification channel that an SoC uses
separate from the rx path, use the same.
Signed-off-by: Nishanth Menon <[email protected]>
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The clock composite is required when using the clock framework. So
select it automatically.
Signed-off-by: Heiko Thiery <[email protected]>
Reviewed-by: Giulio Benetti <[email protected]>
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When regulator consumer attempts to set enabled DVS regulator voltage,
the driver aborts with "Only DVS bucks can be changed when enabled".
In case the regulator is already set to specified voltage, do nothing
instead of failing outright.
When regulator consumer attempts to set enables regulator which cannot
be controlled because it is already always enabled, the driver aborts
with -EINVAL. Again, do nothing in such case and return 0, because the
request is really fulfilled, the regulator is enabled.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Matti Vaittinen <[email protected]>
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Initial support for Fairchild's 8 bit I2C gpio expander FXL6408.
The CONFIG_FXL6408_GPIO define enables support for such devices.
Based on: https://patchwork.kernel.org/patch/9148419/
Signed-off-by: Oleksandr Suvorov <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Marcel Ziswiler <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
Signed-off-by: Oleksandr Suvorov <[email protected]>
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The value of cnt is overwritten without being used.
Signed-off-by: Haolin Li <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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After acking the requested frequency, should wait the ack bit clear
by DDR controller and check the DFS interrupt for next request polling.
Otherwise, the next polling of request bit will get previous value
that DDR controller have not cleared it, so a wrong request frequency
is used.
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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