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Move unnecessary clock frequency assignment out of device-tree and into the
board config header so that the ns16550 serial driver can successfully init
during SPL after failing to resolve the parent clock from upstream dts. The
serial driver will then resolve clock frequency from device-tree node parent
clock at init during Main app as it is expected by upstream.
Signed-off-by: E Shattow <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Distro boot scripts are deprecated. Use standard boot instead.
Signed-off-by: Nam Cao <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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device tree overlay support requires fdtoverlay_addr_r to be set
before
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Invalid fdtoverlay_addr_r for loading overlays
after
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Retrieving file: /boot/overlay/rtc-ds3231.dtbo
Signed-off-by: John Clark <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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boot from SDIO3.0 (mmc sdcard) first if it is plugged.
If mmc is not plugged try to boot from emmc if it is plugged.
If emmc is not plugged then try to boot from nvme.
Signed-off-by: Milan P. Stanić <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Make NVMe and USB target boot devices on the StarFive VisionFive 2 board.
The boot devices are sorted by decreasing device speed.
CONFIG_PCI_INIT_R=y is set via [1]. 'start usb' is added to CONFIG_PREBOOT
by the same patch.
[1] [PATCH v1 1/2] configs: starfive: Enable PCIE auto enum and NVME/USB stuff for Starfive Visionfive 2
https://lore.kernel.org/u-boot/TY3P286MB2611C9AD6E5BB3756A959E89981FA@TY3P286MB2611.JPNP286.PROD.OUTLOOK.COM/
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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This RISC-V ACLINT specification [1] defines a set of memory mapped
devices which provide inter-processor interrupts (IPI) and timer
functionalities for each HART on a multi-HART RISC-V platform.
The RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, however the device tree binding
is a new one. This change updates the sifive clint timer driver to
support ACLINT mtimer device, using a per-driver data field to hold
the mtimer offset to the base address encoded in the mtimer node.
[1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
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Add board support for StarFive VisionFive v2.
Signed-off-by: Yanhong Wang <[email protected]>
Tested-by: Conor Dooley <[email protected]>
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