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11 days[ARCH/RISC-V] Next RISC-V (#10320)GUI
* [libcpu][risc-v] Refactor the RISC-V architecture port Introduce an opt-in unified RISC-V common layer for RV32 and RV64 while keeping existing BSPs on the legacy implementation during migration. - use ARCH_RISCV and ARCH_CPU_64BIT for architecture and XLEN selection - unify context, trap, MMU, cache, timer, SBI, SMP and ISA handling - add PLIC, CLIC, ACLINT, APLIC and IMSIC support - map physical hart IDs to contiguous logical CPU IDs - add T-Head vendor overrides while preserving legacy ports - migrate qemu-virt64-riscv with RV32 and RV64 support - update clock_time, MM, LWP, OFW, PCI and Rust integration Existing BSPs continue using legacy_common or common64 unless they select RT_USING_RISCV_NEW_COMMON. Signed-off-by: GuEe-GUI <[email protected]> * [libcpu][risc-v] skip disabled CPU nodes in early FDT walk Rbb666 noted that rt_hw_fdt_install_early() walked every /cpus child without checking status, so disabled cores still joined hart registration and MMU capability probing. Skip nodes that are not okay/ok via rt_fdt_device_is_available() before reading reg or mmu-type. Signed-off-by: seteiro <[email protected]> * [libcpu][risc-v] Fix per-CPU page table mapping - reuse existing non-leaf page table entries when mapping per-CPU areas - reject leaf entry conflicts instead of overwriting mappings Signed-off-by: GuEe-GUI <[email protected]> --------- Signed-off-by: GuEe-GUI <[email protected]> Signed-off-by: seteiro <[email protected]> Co-authored-by: seteiro <[email protected]>
2026-06-15[dm][virtio] support virtio dmGuEe-GUI
1. version for v1.2 2. support packed queue 1. support MMIO/PCI over bus 2. new virtio queue api with dma/cpu sync 3. update for virtio device drivers: - net - block - console - input - gpu 4. new virtio device drivers: - 9p - crypto - rng - scmi - scsi Signed-off-by: GuEe-GUI <[email protected]>
2025-01-10bsp: qemu-virt64-riscv: remove config RISCV_S_MODEChen Wang
RISCV_S_MODE configuration only affects the code in libcpu/risc-v/virt64, and the only bsp using this libcpu is qemu-virt64-riscv. Considering s-mode is the default mode RT-Thread running on virt64 machine, it seems unnecessary to make RISCV_S_MODE a Kconfig option. Solution: Remove RISCV_S_MODE from Kconfig and define it as a macro in the code in libcpu/risc-v/virt64. Plus, due to this macro is only related to virt64, rename RISCV_S_MODE to RISCV_VIRT64_S_MODE. Update the .config/rtconfig.h in this patch. Signed-off-by: Chen Wang <[email protected]>
2024-12-25bsp: qemu-virt64-riscv: Kconfig: remove duplicated RT_USING_VIRTIOChen Wang
There is problem in the Kconfig of qemu-virt64-riscv. RT_USING_VIRTIO is already defined in components/drivers/virtio/Kconfig, so it should not be defined again in the BSP kconfig. The solution is to rename RT_USING_VIRTIO to BSP_USING_VIRTIO. Also, refer to the configuration method for virtio device drivers in bsp/qemu-virt64-aarch64/drivers/Kconfig to rewrite the configuration of BSP_USING_VIRTIO_xxx. Updated default .config/rtconfig.h at the same time. Signed-off-by: Chen Wang <[email protected]>
2024-11-20[bsp][qemu-virt64-riscv]:remove the redundant UART1 configuration from the ↵zhangjing
Kconfig
2022-12-03sync branch rt-smart. (#6641)guo
* Synchronize the code of the rt mart branch to the master branch. * TTY device * Add lwP code from rt-smart * Add vnode in DFS, but DFS will be re-write for rt-smart * There are three libcpu for rt-smart: * arm/cortex-a, arm/aarch64 * riscv64 Co-authored-by: Rbb666 <[email protected]> Co-authored-by: zhkag <[email protected]>
2022-05-25[bsp] rename qemu-riscv-virt64 to qemu-virt64-riscvrewine