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-rw-r--r--ports/cortex_m0/iar/src/tx_thread_schedule.s25
1 files changed, 23 insertions, 2 deletions
diff --git a/ports/cortex_m0/iar/src/tx_thread_schedule.s b/ports/cortex_m0/iar/src/tx_thread_schedule.s
index 02c60b6e..e4bac172 100644
--- a/ports/cortex_m0/iar/src/tx_thread_schedule.s
+++ b/ports/cortex_m0/iar/src/tx_thread_schedule.s
@@ -28,6 +28,10 @@
EXTERN _tx_thread_preempt_disable
EXTERN _tx_execution_thread_enter
EXTERN _tx_execution_thread_exit
+#ifdef TX_LOW_POWER
+ EXTERN tx_low_power_enter
+ EXTERN tx_low_power_exit
+#endif
;
;
SECTION `.text`:CODE:NOROOT(2)
@@ -37,7 +41,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M0/IAR */
-;/* 6.1 */
+;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -70,7 +74,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
-;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
+;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
+;/* 03-02-2021 Scott Larson Modified comment(s), add */
+;/* low power code, */
+;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -238,11 +245,25 @@ __tx_ts_wait:
STR r1, [r0] ; Store it in the current pointer
CMP r1, #0 ; If non-NULL, a new thread is ready!
BNE __tx_ts_ready ;
+
+#ifdef TX_LOW_POWER
+ PUSH {r0-r3}
+ BL tx_low_power_enter ; Possibly enter low power mode
+ POP {r0-r3}
+#endif
+
#ifdef TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
#endif
+
+#ifdef TX_LOW_POWER
+ PUSH {r0-r3}
+ BL tx_low_power_exit ; Exit low power mode
+ POP {r0-r3}
+#endif
+
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;