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dwc2_info.py
Age
Commit message (
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Author
2026-04-10
clean up
hathach
2026-04-09
rename ep_fifo_size (bytes) to otg_dfifo_depth (words)
hathach
2026-03-28
Add nrf54lm20 dwc2 info
gab-k
2026-02-13
add CFG_TUD_VBUS_SENSE, that could allow to skip tud_configure() for fixed ↵
hathach
vbus sensing simplify dwc2_stm32_gccfg_cfg() using guid value
2025-12-01
add linkermap to deps and linkermap taget
hathach
2025-09-15
add nrf54 to dwc2 info
hathach
2025-09-03
add at32f415 dwc2 info
hathach
2025-08-07
update at32f405 dwc2 info and phy width selection
hathach
2025-06-12
Merge branch 'master' into fork/james-advatek/stm32n657nucleo
hathach
2025-06-11
add h7rs to ci matrix
hathach
2025-06-04
chore: squash previous commits from other branches
James Sandison
2025-01-24
Add NUCLEO-H7S3L8 BSP.
HiFiPhile
Signed-off-by: HiFiPhile <
[email protected]
>
2024-11-11
correctly test dwc2 dma device for s3, disable for p4 (cache issue) and f407 ↵
hathach
fs (slave only)
2024-10-28
implement hcd_edpt_abort_xfer, hcd_device_close,
hathach
check request queue available before making usb attempt. Though there is no handling when queue is full. device_info example work well
2024-10-25
more progress on dwc2 hcd, initial code for edpt xfer
hathach
2024-10-21
add tusb_time_millis(), able to reset and enable dwc2 port and get SOF active
hathach
2024-10-10
add f407disco to hil pool
hathach
2024-10-10
improving dwc2, merging diep and doep if possible
hathach
2024-10-10
enhance dwc2 markdown with field mapping
hathach
2024-10-07
Merge pull request #2809 from shuffle2/master
Ha Thach
make all python files executable and standardize interpreter
2024-09-30
added p4, seems to work well and enumerated
hathach
2024-09-30
update/rename ghwcfg registers
hathach
2024-09-30
update to dwc2 register struct
hathach
2024-09-17
make all python files executable and standardize interpreter
Shawn Hoffman
2023-11-22
add spec version to dwc2 info
hathach
2023-11-19
Fix CI
HiFiPhile
2023-11-19
Add dwc2 info of F429.
HiFiPhile
2023-10-30
addd dwc2_info.py/md update stm32u5a5 board clock & power configure, able to ↵
hathach
get passed otg clock reset
