| Age | Commit message (Collapse) | Author |
|---|
|
This adds support for the MT8390 EVK board with the following
features enabled/tested: Boot, UART, Watchdog and MMC.
MT8390 is based on MT8188.
Signed-off-by: Julien Masson <[email protected]>
Signed-off-by: Julien Stephan <[email protected]>
Reviewed-by: Mattijs Korpershoek <[email protected]>
|
|
Ozan Durgut <[email protected]> says:
This series introduces updates for Analog Devices SC5xx boards.
It cleans up device trees by renaming GPIO expanders and removing
incorrect SPI flash definitions from the common include file.
For the SC598, this series updates the EZLITE board to the latest
Revision E hardware. It also adds missing GPIO hogs and enables
additional commands for the EZKIT configuration.
Link: https://lore.kernel.org/r/[email protected]
|
|
Update the SC598 SOM EZLITE device tree to use the latest revision of
the System on Module (Rev E).
Signed-off-by: Ozan Durgut <[email protected]>
Reviewed-by: Greg Malysa <[email protected]>
|
|
The current naming convention for GPIO expanders across ADI SC5xx
device trees is inconsistent. This patch updates the node names to
correct indexing and clarify hardware location.
For SC573, SC584, and SC589 evaluation SBCs, switch to zero-based
indexing to align with standard conventions.
For SC594 and SC598 SoM + carrier evaluation kits, rename the nodes to
crr_gpio_expander. This prefix indicates which board the expander is on.
Signed-off-by: Ozan Durgut <[email protected]>
Reviewed-by: Greg Malysa <[email protected]>
|
|
SPI flash devices are not common across all SC5xx boards. They
already defined in the SoM-specific dtsi files. Keeping the
definition in the common dtsi is therefore incorrect.
Fixes: c9e893d ("board: adi: Add support for SC598")
Signed-off-by: Philip Molloy <[email protected]>
Signed-off-by: Ozan Durgut <[email protected]>
Reviewed-by: Greg Malysa <[email protected]>
|
|
Add missing GPIO hogs for UART0 enable, UART0 flow control,
SD Card and eMMC control signals.
Fixes: c9e893d ("board: adi: Add support for SC598")
Signed-off-by: Ozan Durgut <[email protected]>
Reviewed-by: Greg Malysa <[email protected]>
|
|
Enable FAT and GPT support, as well as mtd and wget commands
Signed-off-by: Ozan Durgut <[email protected]>
Reviewed-by: Greg Malysa <[email protected]>
|
|
Ernest Van Hoecke <[email protected]> says:
This is a small, board-specific series for Aquila AM69.
Patch 1 fixes intermittent SPL USB DFU gadget enumeration.
Patch 2 drops a stale MCU_CLKOUT0 enable for ETH_1. V1.1 hardware uses
an external 25 MHz crystal, and support for earlier revisions was
already removed from the DT before upstreaming.
Link: https://lore.kernel.org/r/[email protected]
|
|
On the Toradex Aquila AM69 V1.1, the on-module ETH_1 relies on an
external 25 MHz crystal oscillator. On the V1.0, we needed to enable
MCU_CLKOUT0, but support for this was already dropped from the device
tree before being sent to U-Boot.
Remove this obsolete enabling of MCU_CLKOUT0.
Fixes: 3f0528882c0d ("board: toradex: add aquila am69 support")
Signed-off-by: Ernest Van Hoecke <[email protected]>
Reviewed-by: Francesco Dolcini <[email protected]>
|
|
Around 1 in 20 times, the current R5 SPL fails to pull up the D+ line to
signal that a new USB device (the USB gadget used for downloading the
next stage) joined the bus.
With these strapping options, this is greatly reduced to 1 in thousands.
Link: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1587424/am69-u-boot-spl-usb-dfu-cdns3-occasionally-fails-to-pull-up-d-in-cdns3_gadget_config
Fixes: 3f0528882c0d ("board: toradex: add aquila am69 support")
Signed-off-by: Ernest Van Hoecke <[email protected]>
Reviewed-by: Francesco Dolcini <[email protected]>
|
|
The H6/H616 boot ROM doesn't expect a SPL scrambled the same way as
older SoCs.
It doesn't use a specific seeds table, it expects a maximized ECC
(BCH-80), a specific BBM (FF000301) and doesn't work if empty pages are
skipped (it needs its specific BBM, even in the padding).
So, add a --soc=h6 option to support H6/616 with:
- more ECC strengths
- specific BBM
- default_scrambler_seeds[] with all values
- no empty pages skip
In Kconfig, select BCH-80 by default for SUNXI_SPL_ECC_STRENGTH to make
BROM happy.
And in scripts/Makefile.xpl, use --soc=h6 option when building for a
SUN50I_GEN_H6 SoC.
Tested on Whatsminer H616 board, booting from NAND.
Reviewed-by: Miquel Raynal <[email protected]>
Co-developed-by: James Hilliard <[email protected]>
Signed-off-by: James Hilliard <[email protected]>
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
|
|
The MACRO NFC_PAGE_SHIFT(x) already deals with removing 10 from
nand->page_shift, so it shouldn't be done twice.
Fixes: 4ccae81cdadc ("mtd: nand: Add the sunxi NAND controller driver")
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
|
|
Fix a cast to pointer from integer warning on ARM64
On 64bits platform, the casts done in {read,write}l() give that kind of
warnings:
drivers/mtd/nand/raw/sunxi_nand_spl.c: In function ‘check_value_inner’:
./arch/arm/include/asm/io.h:110:43: warning: cast to pointer from \
integer of different size [-Wint-to-pointer-cast]
110 | #define __raw_readl(a) (*(volatile unsigned int *)(a))
| ^
[...]
drivers/mtd/nand/raw/sunxi_nand_spl.c:81:27: note: in expansion of \
macro ‘readl’
81 | int val = readl(offset) & expected_bits;
Introduce {read,write}l_nfc inline function to do the right cast and
push the base address (SUNXI_NFC_BASE) into those functions, making the
code more readable.
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
|
|
Introduce H6/H616 NAND controller support for SPL
The H616 NAND controller has the same base as A10/A23, with some
differences:
- MDMA is based on chained buffers
- its ECC supports up to 80bit per 1024bytes
- some registers layouts are a bit different, mainly due do the stronger
ECC.
- it uses USER_DATA_LEN registers along USER_DATA registers.
- it needs a specific clock for ECC and MBUS.
For SPL, most of the work was setting the clocks, adding the new
capability structure for H616 and supporting the new USER_DATA_LEN
registers.
Tested on Whatsminer H616 board (with and without scrambling, ECC)
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
|
|
Introduce H6/H616 NAND controller support for U-Boot
The H616 NAND controller has the same base as A10/A23, with some
differences:
- MDMA is based on chained buffers
- its ECC supports up to 80bit per 1024bytes
- some registers layouts are a bit different, mainly due do the stronger
ECC.
- it uses USER_DATA_LEN registers along USER_DATA registers.
- it needs a specific clock for ECC and MBUS.
Introduce the basic support, with ECC and scrambling, but without
DMA/MDMA.
Tested on Whatsminer H616 board (with and without scrambling, ECC)
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
|
|
Add MBUS Master Clock Gating Register for H6 and H616
For H6/H616, the NAND controller needs the MBUS NAND clock along with
CLK_NAND0/1 and CLK_BUS_NAND.
The bit locations are from H6/H616 User Manuals.
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
|
|
Add missing NAND controller-related clock registers
The NAND controller on H6/H616 uses one clock for its internal logic
(NAND0_CLK) and one clock for ECC engine (NAND1_CLK) in addition to AHB
and MBUS clocks.
As NAND{0,1}_CLKs and MBUS_GATE are missing, add them.
The bit locations are from H616/H6 User Manual.
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
|
|
Use generic macros for ECC_MODE and RANDOM_SEED
As H6/H616 registers are different, use more generic macros than hard
coded values specific to A10-like SoC.
No functional changes.
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
|
|
Increase max_oobsize to take into account bigger OOB on 2KiB pages
Some NAND chip (e.g. Kioxia TC58NVG1S3HTA00) have a 2KiB page size +
128 bytes OOB.
In order to detect them, the max_oobsize has to be increased from 64 to
128 bytes.
Tested on Kioxia TC58NVG1S3HTA00 NAND chip on Whatsminer H616 board.
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
|
|
Use defines instead of hardcoded values for NFC_ECC_{ERR_MSK,PAT_FOUND}
SPL is using hard coded values for ECC error detection and empty chunk
detection.
The H6/H616 registers for that have changed, the pattern found is no
more in the NFC_REG_ECC_ST register.
So, don't presume anymore that pattern_found is in NFC_REG_ECC_ST, and
read the pattern_found register to get this information.
Apart from an additional register reading, no functional change.
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
|
|
Introduce NDFC Spare Area Register offset in SoC capabilities
The H6/H616 spare area register is not at the same offset as the
A10/A23 one, so move its offset into sunxi_nfc_caps.
No functional change.
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
|
|
NFC_RANDOM_{EN,DIRECTION} registers offset moved in H616
Let's make it a SoC capability.
NFC_RANDOM_DIRECTION also moved, but it's unused, just remove it.
No functional change.
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
|
|
Introduce per SoC capabilities in sunxi_nand_spl.c
Prepare for the H616 support that has quite a lot of differences in
registers offset and capabilities.
Start with the 512 bytes ECC capability.
No functional change.
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
|
|
Introduce NDFC Pattern ID Register in capability structure
The H6/H616 pattern ID register is not at the same offset as the
A10/A23 one, so move its offset into sunxi_nfc_caps.
No functional change.
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
|
|
NFC_ECC_MODE register offset moved in H616, so let's make it a SoC cap
No functional change.
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
|
|
Introduce has_ecc_block_512 capability
The H616 controller can't handle 512 bytes ECC block size. The
NFC_ECC_BLOCK_512 bit disappeared in H6, and NDFC_RANDOM_EN took its
place.
So, add has_ecc_block_512 capability to only set this bit on SoC having
it.
On the way, let's drop NFC_ECC_BLOCK_SIZE_MSK which was just a mask for
the very same bit.
No functional change.
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
|
|
Move ECC_PAT_FOUND register in SoC capabilities structure
This register offset moved in H616, it's now its own register (@0x3c,
bits 0-31), not shared with NFC_ECC_ST any more (was @0x38 bits 16-31).
Push that specificity in caps structure.
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
|
|
USER_DATA register offset moved in H616, so let's make it a SoC cap
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
|
|
ECC_ERR_CNT register offset moved in H616, so let's make it a SoC cap
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
|
|
Introduce per SoC capabilities in sunxi_nand.c
This prepares for the H616 support that has quite a lot differences in
registers offset and capabilities.
Start with the ECC strength table.
No functional change.
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
|
|
Merge common register definitions from sunxi_nand{,_spl}.c
The Allwinner NAND controller registers where in both files, so let's
just merge all that in a header, it will be easier for maintenance.
NB: the defines are also harmonized with Linux driver
No functional change
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
|
|
The sunxi_ccm_reg is legacy, drop its usage from nand related code
For that, CCU_NAND0_CLK_CFG and CCU_AHB_GATE1 are added to the clock
files when missing.
And clock code in sunxi_nand{,_spl}.c and board.c are changed to use the
new scheme.
Moreover, drop AHB_DIV_1 in favor of the more readable CCM_NAND_CTRL_M/N
Suggested-by: Andre Przywara <[email protected]>
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
|
|
Remove unneeded definitions NFC_CMD_R* in sunxi_nand_spl.c
No need to define NFC_CMD_RNDOUTSTART, NFC_CMD_RNDOUT and
NFC_CMD_READSTART here since they are already in linux/mtd/rawnand.h
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
|
|
Harmonize registers definition in sunxi_nand{,_spl}.c files
This is a first step to then include the same file from both
sunxi_nand{,_spl}.c files
Unused defines are also removed
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
|
|
Fix pointer from interget warning when compiling for ARM64
When compiling for arm64, we get this error:
error: passing argument 2 of ‘__memcpy_fromio’ makes pointer from
integer without a cast [-Wint-conversion]
Moreover the copy should be made with dedicated readl(), like for any
register access on this peripheral, since they are 32bit wide.
So, instead of memcpy_fromio(), just use a readl() loop.
Introduce nand_readlcpy() to implement this loop.
Fixes: 6ddbb1e936c7 ("spl: nand: sunxi: use PIO instead of DMA")
Suggested-by: Andre Przywara <[email protected]>
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
|
|
Remove 'complete' member from struct sunxi_nfc
The 'complete' member isn't part of the structure, let's remove it.
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
|
|
When compiled with FTRACE=1 U-boot will crash as %rdi is clobbered
in board_init_f_alloc_reserve() and board_init_f_init_reserve() will
memset the .text segment instead of the global_data struct.
According to the System V AMD64 ABI %rdi is not preserved and the
existing code only worked as board_init_f_alloc_reserve() was small
enough to not use %rdi.
Fix that by always passing the correct argument to
board_init_f_init_reserve().
TEST=Can boot on qemu-q35 with FTRACE=1 enabled during build.
Signed-off-by: Patrick Rudolph <[email protected]>
|
|
The else if branch uses the is_zimage boolean which is initialized to 0
and never set before being tested here.
remove the test on is_zimage to make this code reachable.
Signed-off-by: Guillaume Ranquet <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
Allow the system to reset the CPU without calling the reset
controller. This patch also removed the default SYSRESET controller
for MT7628, as it is now optional.
Signed-off-by: Shiji Yang <[email protected]>
|
|
Mediatek MT7620 u-boot does not have PINCONF implementation.
Signed-off-by: Shiji Yang <[email protected]>
|
|
Excessive default value causes crash on hardware: x86 baytrail E3845
It is unclear where the data is being populated being 'BLOBLISTT_TCPA_LOG'
is not found elsewhere in the u-boot tree. This leads to confusion about
how much space for TPM log is actually needed.
This was tested on hardware using TPMv1.
Signed-off-by: Eric Schikschneit <[email protected]>
|
|
https://source.denx.de/u-boot/custodians/u-boot-mmc
- Add DMA support for mediatek mmc
- Cleanup mmc cmd
- Fix typos in mmc
[trini: Fix "quoted string split across lines" checkpatch warning]
Signed-off-by: Tom Rini <[email protected]>
|
|
My Linaro email address is no longer valid. Update entries in the
MAINTAINERS file, and add a mapping in the mailmap file.
Signed-off-by: Sughosh Ganu <[email protected]>
|
|
Return symbolic value CMD_RET_FAILURE instead of literal "1" when
failing to switch the partition to improve readability.
Signed-off-by: Yao Zi <[email protected]>
Tested-by: Anshul Dalal <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
Currently when any of speed_mode, part, or dev fails to be parse as a
number, no error is reported. In this case __init_mmc_device() is called
with weird arguments, probably zeroes if there's no digit prefixing the
argument, which is especially confusing when the invocation occasionally
succeeds.
Let's check whether arguments are valid numbers without trailing
characters. This is quite helpful for speed_mode: it requires an index
instead of a mode name, one may easily pass in a string, which will be
parsed as zero (MMC_LEGACY), without carefully reading the
documentation, then finds the MMC device is under an unexpected mode.
Signed-off-by: Yao Zi <[email protected]>
Tested-by: Anshul Dalal <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
Replace the big if-else block in do_mmc_dev() with switch-case and use
fallthrough to remove the duplicated code for parsing dev and part.
Signed-off-by: Yao Zi <[email protected]>
Tested-by: Anshul Dalal <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
Fix the following typos in drivers/mmc/mmc.c:
- "neiter" -> "neither" in __mmc_switch() comment
- "witdh" -> "width" in bus_width() warning message
- "enver" -> "never" in mmc_select_mode_and_width() comment
Signed-off-by: Tanmay Kathpalia <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
Implement DMA support in the MediaTek MMC driver to enhance data
transfer speed.
- Define DMA control and configuration registers
- Implement functions for starting, stopping, and completing DMA
transfers
- Modify data transfer logic to utilize DMA when enabled
- Ensure proper cache management during DMA operations
Signed-off-by: Wenbin Mei <[email protected]>
Signed-off-by: ht.lin <[email protected]>
Signed-off-by: Julien Masson <[email protected]>
Signed-off-by: Macpaul Lin <[email protected]>
Signed-off-by: David Lechner <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
Indent a brace for proper code style.
Signed-off-by: David Lechner <[email protected]>
Reviewed-by: Macpaul Lin <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
Replace separate mask and shift definitions with GENMASK and FIELD_*
macros for better readability and maintainability.
All macros ending in _M have the suffix dropped. The value remains the
same but is now generated with GENMASK. All macros ending in _S are
removed and their uses replaced with FIELD_PREP and FIELD_GET macros.
Signed-off-by: David Lechner <[email protected]>
Reviewed-by: Macpaul Lin <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
