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Age	Commit message (Collapse)	Author
2017-07-12	imx: reorganize IMX code as other SOCs	Stefano Babic
	Change is consistent with other SOCs and it is in preparation for adding SOMs. SOC's related files are moved from cpu/ to mach-imx/<SOC>. This change is also coherent with the structure in kernel. Signed-off-by: Stefano Babic <[email protected]> CC: Fabio Estevam <[email protected]> CC: Akshay Bhat <[email protected]> CC: Ken Lin <[email protected]> CC: Marek Vasut <[email protected]> CC: Heiko Schocher <[email protected]> CC: "Sébastien Szymanski" <[email protected]> CC: Christian Gmeiner <[email protected]> CC: Stefan Roese <[email protected]> CC: Patrick Bruenn <[email protected]> CC: Troy Kisky <[email protected]> CC: Nikita Kiryanov <[email protected]> CC: Otavio Salvador <[email protected]> CC: "Eric Bénard" <[email protected]> CC: Jagan Teki <[email protected]> CC: Ye Li <[email protected]> CC: Peng Fan <[email protected]> CC: Adrian Alonso <[email protected]> CC: Alison Wang <[email protected]> CC: Tim Harvey <[email protected]> CC: Martin Donnelly <[email protected]> CC: Marcin Niestroj <[email protected]> CC: Lukasz Majewski <[email protected]> CC: Adam Ford <[email protected]> CC: "Albert ARIBAUD (3ADEV)" <[email protected]> CC: Boris Brezillon <[email protected]> CC: Soeren Moch <[email protected]> CC: Richard Hu <[email protected]> CC: Wig Cheng <[email protected]> CC: Vanessa Maegima <[email protected]> CC: Max Krummenacher <[email protected]> CC: Stefan Agner <[email protected]> CC: Markus Niebel <[email protected]> CC: Breno Lima <[email protected]> CC: Francesco Montefoschi <[email protected]> CC: Jaehoon Chung <[email protected]> CC: Scott Wood <[email protected]> CC: Joe Hershberger <[email protected]> CC: Anatolij Gustschin <[email protected]> CC: Simon Glass <[email protected]> CC: "Andrew F. Davis" <[email protected]> CC: "Łukasz Majewski" <[email protected]> CC: Patrice Chotard <[email protected]> CC: Nobuhiro Iwamatsu <[email protected]> CC: Hans de Goede <[email protected]> CC: Masahiro Yamada <[email protected]> CC: Stephen Warren <[email protected]> CC: Andre Przywara <[email protected]> CC: "Álvaro Fernández Rojas" <[email protected]> CC: York Sun <[email protected]> CC: Xiaoliang Yang <[email protected]> CC: Chen-Yu Tsai <[email protected]> CC: George McCollister <[email protected]> CC: Sven Ebenfeld <[email protected]> CC: Filip Brozovic <[email protected]> CC: Petr Kulhavy <[email protected]> CC: Eric Nelson <[email protected]> CC: Bai Ping <[email protected]> CC: Anson Huang <[email protected]> CC: Sanchayan Maity <[email protected]> CC: Lokesh Vutla <[email protected]> CC: Patrick Delaunay <[email protected]> CC: Gary Bisson <[email protected]> CC: Alexander Graf <[email protected]> CC: [email protected] Reviewed-by: Fabio Estevam <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
2016-12-16	imx-common: cache: configure L2 Cache for i.MX6SLL	Peng Fan
	If L2 cache configured as OCRAM, reset it. Switch to use runtime check. Signed-off-by: Peng Fan <[email protected]> Cc: Stefano Babic <[email protected]>
2016-05-06	imx6: cache: disable L2 before touching Auxiliary Control Register	Peng Fan
	According PL310 TRM, Auxiliary Control Register " The register must be written to using a secure access, and it can be read using either a secure or a NS access. If you write to this register with a NS access, it results in a write response with a DECERR response, and the register is not updated. Writing to this register with the L2 cache enabled, that is, bit[0] of L2 Control Register set to 1, results in a SLVERR. " So If L2 cache is already enabled by ROM, chaning value of ACR will cause SLVERR and uboot hang. Signed-off-by: Peng Fan <[email protected]> Cc: Stefano Babic <[email protected]> Cc: Fabio Estevam <[email protected]>
2015-09-13	arm: imx: common rework cache settings for imx6	Adrian Alonso
	Rework cache settings for imx6, move cache configuration to imx-common/cache.c so it can be reused for newer SoC Signed-off-by: Adrian Alonso <[email protected]>