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Move arch/arm/cpu/armv7/exynos/* to arch/arm/mach-exynos/* to allow
reuse of existing code for ARMv8 based Exynos platforms.
Cc: Minkyu Kang <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Masahiro Yamada <[email protected]>
Signed-off-by: Thomas Abraham <[email protected]>
Reviewed-by: Masahiro Yamada <[email protected]>
Tested-by: Przemyslaw Marczak <[email protected]>
Acked-by: Przemyslaw Marczak <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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This patch adds code for clock initialization and clock settings
of various IP's and controllers, required for Exynos5420
Signed-off-by: Rajeshwari S Shinde <[email protected]>
Signed-off-by: Akshay Saraswat <[email protected]>
Acked-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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This patch makes the necessary changes for making use of
I2S0 channel instead of I2S1 channel on smdk board. This
changes are done to maintain the uniformity to use I2S0 channel.
Signed-off-by: Dani Krishna Mohan <[email protected]>
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Signed-off-by: Wolfgang Denk <[email protected]>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <[email protected]>
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This patch adds clock structure for Exynos4x12.
Signed-off-by: Chander Kashyap <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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This patch adds clock support for I2S
Signed-off-by: R. Chandrasekar <[email protected]>
Signed-off-by: Rajeshwari Shinde <[email protected]>
Acked-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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This patch adds support for BPLL clock.
Signed-off-by: Rajeshwari Shinde <[email protected]>
Acked-by: Joonyoung Shim <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz.
Adjust the divisor value to get 800MHz as needed by devices
like UART etc
Signed-off-by: Hatim Ali <[email protected]>
Signed-off-by: Rajeshwari Shinde <[email protected]>
Acked-by: Joonyoung Shim <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Define additional registers for clock control in Exynos5250 Rev 1.0
Signed-off-by: Hatim Ali <[email protected]>
Signed-off-by: Rajeshwari Shinde <[email protected]>
Acked-by: Joonyoung Shim <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Samsung's ARM Cortex-A15 based SoCs are known as Exynos5 series of
SoCs. This patch adds the support for Exynos5.
Signed-off-by: Chander Kashyap <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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As per new naming convention for Samsung SoC's, all Cortex-A9 and Cortex-A15
based SoC's will be classified under the name Exynos. Cortex-A9 and Cortex-A15
based SoC's will be sub-classified as Exynos4 and Exynos5 respectively.
In order to better adapt and reuse code across various upcoming Samsung Exynos
based boards, all uses of s5pc210 prefix/suffix/directory-names are renamed in
this patch. s5pc210 is renamed as exynos4210 and S5PC210/s5pc210 suffix/prefix
are renamed as exynos4/EXYNOS4.
Signed-off-by: Chander Kashyap <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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