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Fix macros for the GPIO function for two pads (ENET1_TD3 and I2C2_SCL),
aligning them to the functions specified in the datasheet.
Fixes: a9d562daa3c3 ("imx: Add iMX91 support")
Suggested-by: Javier Viguera <[email protected]>
Signed-off-by: Francesco Valla <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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Add USB1_BASE_ADDR and USB2_BASE_ADDR for i.MX9 platform, and define
USB_BASE_ADDR as an alias to USB2_BASE_ADDR.
Signed-off-by: Alice Guo <[email protected]>
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Due to i.MX95 has reserved first 256MB DDR, change to use the DDR
start address in u-boot as the container header buffer.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Alice Guo <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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i.MX94
- Add base addresses for WDG3, WDG4, GPIO6, and GPIO7 for i.MX94.
- Introduce common.h with macros of clock IDs, power domains, and CPU
types for platform-specific replacement (e.g., i.MX94, i.MX95).
- Extend imx_get_mac_from_fuse() to support i.MX94.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Alice Guo <[email protected]>
Acked-by: Peng Fan <[email protected]>
Reviewed-by: Jacky Bai <[email protected]>
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reasons
System Manager provides the last booted and shutdown reasons of the
logical machines (LM) and system using the SCMI misc protocol (Protocol
ID: 0x84, Message ID: 0xA). This path adds get_reset_reason() to query
and print these reasons in SPL and U-Boot.
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Alice Guo <[email protected]>
Reviewed-by: Ye Li <[email protected]>
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The LPCG number on iMX93 and iMX91 is 127 not 122. The wrong
value is used in ccm_reg structure and Coverity reports several
issues as out-of-bounds write.
Signed-off-by: Ye Li <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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Reuse and export low_drive_freq_update() function. This way global imx9
board_fix_fdt() doesn't duplicate code. While low_drive_freq_update()
can be reused on boards such as phyCORE-i.MX93 (TARGET_PHYCORE_IMX93)
which is not using the global imx9 board_fix_fdt() implementation.
While at it, make printout logic less verbose by only outputting on the
error condition and not on each successful clock fixup. Also drop now
invalid comment (low_drive_freq_update() now does fixup for internal and
kernel device-tree).
Signed-off-by: Primoz Fiser <[email protected]>
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Add the initial board support for the NXP i.MX93 FRDM board:
https://www.nxp.com/design/design-center/development-boards-and-designs/frdm-i-mx-93-development-board:FRDM-IMX93
Based on the NXP U-Boot code.
There were attempts to upstream the board devicetree, but it has not been
accepted upstream yet:
https://lore.kernel.org/linux-arm-kernel/[email protected]/
Once it reaches upstream, we can switch to OF_UPSTREAM.
Signed-off-by: Fabio Estevam <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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This patch adds i.MX95 SoC and clock related code. Because they are
based on SCMI, put them in the scmi subfolder.
Signed-off-by: Alice Guo <[email protected]>
Signed-off-by: Frank Li <[email protected]>
Signed-off-by: Ji Luo <[email protected]>
Signed-off-by: Jindong Yue <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Ranjani Vaidyanathan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
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Drop global ddrphy_trained_csr which maybe different with per board
ddrphy_trained_csr. DDR TOOL generates ddrphy_trained_csr for each
board, using the global ddrphy_trained_csr has risk that values may
be not up to date.
Signed-off-by: Peng Fan <[email protected]>
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iMX91 is reduced part from iMX93 with part number: i.MX9131/11/01
It removed A55_1, M33, MIPI DSI, LVDS, etc.
i.MX9131:
- Support 2.4GT/s DDR and HWFFC at 1.2GT/s
i.MX9121:
- A55 at 800Mhz and DDR at 1600MTS, with low drive mode.
i.MX9111:
- Support 1.6GT/s DDR and HWFFC at 800MT/s
i.MX9101:
- Support 800Mhz ARM clock
- Support 1.6GT/s DDR and HWFFC at 800MT/s
- No parallel display, eQOS, flexcan
Updated Clock/Container/CPU and etc for i.MX91
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Include types.h header for u32, following Linux Coding Style to include
necessary headers.
Signed-off-by: Peng Fan <[email protected]>
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Replace magic number with meaningful macros.
Signed-off-by: Peng Fan <[email protected]>
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Since we use SPEED GRADE fuse to set A55 frequency, remove the
set_arm_core_low_drive_clk function which has hard coded frequency.
And adjust clock_init called sequence and split it to early and late
functions.
Set the authen register in early function, because CCF driver checks
NS bit.
Set bus and core clock in late function, because the fuse read and
SoC type/rev depend on ELE.
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Replace the static CONFIG_IMX9_LOW_DRIVE_MODE with runtime target
voltage mode by checking the part's SPEED GRADE fuse.
SPL will configure to highest A55 speed which is indicated by the SPEED
fuse and select corresponding voltage mode.
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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To support OSCCA enabled part which has disabled FSB access from SOC,
change directly read from FSB to use fuse_read API.
Signed-off-by: Peng Fan <[email protected]>
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On OSCCA part, M33 TCM is used for ROM PATCH and protected by ELE ROM.
So after release TRDC, we need to configure TRDC for M33 TCM,
otherwise A55 can't access the TCM.
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
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SSAR handshake done means power on finished, not ISO done. so correct
the waiting mask.
Fixes: 0256577a83b ("imx: imx9: Add MIX power init")
Signed-off-by: Peng Fan <[email protected]>
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Since the event callback imx9_probe_mu is re-defined, update
its prototype.
Signed-off-by: Ye Li <[email protected]>
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Put imx9_probe_mu declaration in a new mu.h header file.
Signed-off-by: Mathieu Othacehe <[email protected]>
Reviewed-by: Igor Opaniuk <[email protected]>
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Add support for the Variscite VAR-SOM-IMX93 evaluation kit. The SoM
consists of an NXP iMX93 dual A55 CPU. The SoM is mounted on a Variscite
Symphony SBC.
Signed-off-by: Mathieu Othacehe <[email protected]>
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Per NXP requirement, we rename all the NXP EdgeLock Secure Enclave
code including comment, folder and API name to ELE to align.
Signed-off-by: Peng Fan <[email protected]>
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Signed-off-by: Tom Rini <[email protected]>
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It seems like the header inclusion guards for some IMX related headers
were misspelled or got out of sync.
Make the preprocessor symbols for the #ifndef and #define lines the
same, so that the double inclusion protection works as expected.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Update the DDR init flow for multi-setpoint support on i.MX93. A new
fsp_cfg struct need to be added in the timing file to store the diff
part of the DDRC and DRAM MR register for each setpoint.
Signed-off-by: Jacky Bai <[email protected]>
Reviewed-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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According to DDRPHY errata, the Rank-to-Rank Spacing and tphy_rdcsgap
specification does not include the Critical Delay Difference (CDD) to
properly define the required rank-to-rank read command spacing after
executing PHY training firmware.
Following the errata workaround, at the end of data training, we get
all CDD values through the MessageBlock, then re-configure the DDRC
timing of WWT/WRT/RRT/RWT with comparing MAX CDD values.
Signed-off-by: Ye Li <[email protected]>
Acked-by: Peng Fan <[email protected]>
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Get the chip's market segment and speed grading from fuse and print
them in boot log as other i.MX series.
Signed-off-by: Peng Fan <[email protected]>
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Simplify the clk root settings with an array
Signed-off-by: Peng Fan <[email protected]>
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Use common file ele_ahab.c for i.MX9 and iMX8ULP AHAB support, since
both of them use same sentinel ELE APIs
Signed-off-by: Ye Li <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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Add ethernet support
Signed-off-by: Peng Fan <[email protected]>
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Set ARM clock to OD frequency 1.7Ghz, since we have set PMIC VDD_SOC
to Overdrive voltage 0.9V
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common
directory under imx, then use dedicated ddr controller driver for each
iMX9 and iMX8M.
The DDRPHY registers are space compressed, so it needs conversion to
access the DDRPHY address. Introduce a common PHY address remap function
for both iMX8M and iMX9 for all PHY registers accessing.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Implement the DDR driver clock interfaces for set DDR rate and
bypass DDR PLL
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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To support on-demand booting M33 image from A core. SPL needs
to follow M33 kick up sequence to release M33 firstly,
then set M33 CPUWAIT signal. ATF will clear CPUWAIT to kick
M33 to run.
The prepare function also works around the M33 TCM ECC issue by
clean the TCM. Also enable sentinel handshake and WDOG1 clock
for M33 stop and reset.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Add power init of MEDIAMIX, MLMIX and DDRMIX. And clear isolation
of MIPI DSI/CSI, USBPHY after the power up.
SPL should call the power init in its boot sequence before accessing
above three MIX and USB.
Signed-off-by: Peng Fan <[email protected]>
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Add GPIO registers structure for iMX93, so that we can enable lpgpio
driver
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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i.MX93 fuse can be accessed through FSB and s400-api. Add mapping tables
for i.MX93. The offset address of FSB accessing OTP shadow registers is
different between i.MX8ULP and i.MX93, so use macro to define the offset
address instead of hardcode.
Signed-off-by: Alice Guo <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Add TRDC driver to iMX9. The TRDC init splits to two phases:
1. Early init phase will release TRDC from Sentinel and open write
permission to the memory where SPL image runs. Sentinel will set
the memory to RX only after ROM authentication for the OEM
closed part.
2. Init phase will configure TRDC to allow non-secure master to
access DDR. So the peripherals can work in u-boot.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Support iMX93 communicate with Sentinel
Signed-off-by: Peng Fan <[email protected]>
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Disable all 3 wdogs on AIPS2 and unmask SRC reset trigger for WDOG3-5
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Add timer_init to update ARM arch timer with correct frequency
from system counter and enable system counter.
Signed-off-by: Jian Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Add clock API to support CCM root clock and LPCG setting
Set the CCM AUTHEN register to allow non-secure world to set
root clock and lpcg.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Add i.MX9 Kconfig and basic files for the new SoC
Signed-off-by: Peng Fan <[email protected]>
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