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Move headers to mach-socfpga as well.
Signed-off-by: Masahiro Yamada <[email protected]>
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Since the SoCFPGA SDRAM support is not yet applied to u-boot, we still
need to be able to compile the codebase. Introduce stub functions which
temporarily supplement the missing SDRAM setup functions.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Pavel Machek <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Vince Bridgers <[email protected]>
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Signed-off-by: Dinh Nguyen <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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These functions will be needed for use by the SPL for enabling the
console and sdram initialization.
Signed-off-by: Dinh Nguyen <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Acked-by: Pavel Machek <[email protected]>
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Correctly increment the base address of the freeze controller. And since
SYSMGR_FRZCTRL_VIOCTRL_SHIFT is not needed, remove it from the include file.
Signed-off-by: Dinh Nguyen <[email protected]>
Cc: Vince Bridgers <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Marek Vasut <[email protected]>
Acked-by: Pavel Machek <[email protected]>
Cc: Wolfgang Denk <[email protected]>
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socfpga_scan_manager structure was missing a data member.
Signed-off-by: Dinh Nguyen <[email protected]>
Cc: Vince Bridgers <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Marek Vasut <[email protected]>
Acked-by: Pavel Machek <[email protected]>
Cc: Wolfgang Denk <[email protected]>
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Signed-off-by: Stefan Roese <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Vince Bridgers <[email protected]>
Cc: Marek Vasut <[email protected]>
Acked-by: Pavel Machek <[email protected]>
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This function will be needed by the upcoming Designware master SPI
driver. As the SPI master controller is held in reset by the current
Preloader implementation. So we need to release the reset for the
driver to communicate with the controller.
This function is called from arch_early_init_r() if the SPI
driver is enabled.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Vince Bridgers <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Pavel Machek <[email protected]>
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This patch includes the latest DT sources for socfpga from the current
Linux kernel. And enables CONFIG_OF_CONTROL for the new build target
"socfpga_socrates" (the EBV SoCrates board) to make use of this new DT
support.
Until this patch, the only SoCFPGA U-Boot target in mainline is
"socfpga_cyclone5". This build target is not (yet) changed to support
DT. So nothing changes for this target. Even though the long-term
goal should be to move all SoCFPGA targets over to DT.
One of the reasons to enable DT support in SoCFPGA is, that I need to
support multiple different SPI controllers for this platform. This is
the QSPI Cadence controller and the Designware SPI master controller.
Both are implemented in the SoCFPGA. And enabling both controllers is
only possible by using the new driver model (DM). The DM SPI code
only supports DT based probing. So it was easier to move SoCFPGA to
DT than to add the (deprecated) platform-data based probing to the
DM SPI suport.
Note that the image with the dtb embedded is u-boot-dtb.img. This needs
to be used now for those DT enabled boards instead of u-boot.img.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Vince Bridgers <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Pavel Machek <[email protected]>
Cc: Simon Glass <[email protected]>
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Switch to the common spl.h file and zap the arch/spl.h . Since the arch/spl.h
contained various ad-hoc symbols, zap those symbols as well and rework the
board configuration a little so it doesn't depend on them.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Vince Bridgers <[email protected]>
Cc: Albert Aribaud <[email protected]>
Acked-by: Pavel Machek <[email protected]>
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Add register definition for the NIC-301 used on SoCFPGA.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
Acked-by: Pavel Machek <[email protected]>
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Add the Snoop Control Unit register definition file.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
Acked-by: Pavel Machek <[email protected]>
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Add function to enable and disable FPGA bridges. This code is used
by the FPGA manager to disable the bridges before programming the
FPGA and will later be also used by the initialization code for the
chip to put the chip into well defined state during startup.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
Acked-by: Pavel Machek <[email protected]>
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Add code necessary to program the FPGA part of SoCFPGA from U-Boot
with an RBF blob. This patch also integrates the code into the
FPGA driver framework in U-Boot so it can be used via the 'fpga'
command.
Signed-off-by: Pavel Machek <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
V2: Move the not-CPU specific stuff into drivers/fpga/ and base
this on the cleaned up altera FPGA support.
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Add function to initialize the EMAC blocks upon board startup.
The preprocessor guards against building on SoCFPGA-VT and against
SPL build are not needed as those are handled implicitly via both
SPL framework and the socfpga_cyclone5.h config file, which will
not define CONFIG_DESIGNWARE_ETH if building for SoCFPGA-VT.
We cannot handle two EMAC ethernet blocks yet, therefore the ifdefs.
Once there is hardware using both EMAC blocks, this ifdef will have
to go.
Signed-off-by: Pavel Machek <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
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Add functions to reset the EMAC ethernet blocks. We cannot handle
two EMAC ethernet blocks yet, therefore the ifdefs. Once there is
hardware using both EMAC blocks, this ifdef will have to go.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
Acked-by: Pavel Machek <[email protected]>
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Add the missing pieces from the reference clock code from Altera. This
puts the code on par with the Altera U-Boot fork for all but the SDRAM
self-refresh bits, which are not part of this patch.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
Acked-by: Pavel Machek <[email protected]>
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Clean up the clock code definitions so they are aligned with mainline
standards. There are no functional changes in this patch.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
Acked-by: Pavel Machek <[email protected]>
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Add the entire bulk of code to read out clock configuration from the SoCFPGA
CPU registers. This is important for MMC, QSPI and UART drivers as otherwise
they cannot determine the frequency of their upstream clock.
Signed-off-by: Pavel Machek <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
V2: Fixed the L4 MP clock divider and synced the clock code with latest
rocketboards codebase (thanks Dinh for pointing this out)
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The bit definitions for clock manager are complete chaos. Implement
some basic logical order into them.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
Acked-by: Pavel Machek <[email protected]>
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Clean up the system manager register definition and add the missing
register definitions in place.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
Acked-by: Pavel Machek <[email protected]>
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This adds watchdog disable. It is neccessary for running Linux kernel.
Signed-off-by: Pavel Machek <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
V2: Move RSTMGR_PERMODRST_L4WD0_LSB to reset_manager.h
Reset watchdog only if CONFIG_HW_WATCHDOG is undefined (the default)
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Sort the list of functional block addresses and fix indentation.
No functional change.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
Acked-by: Pavel Machek <[email protected]>
Acked-by: Chin Liang See <[email protected]>
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Add base addresses for all subsystems as documented in the
Cyclone V HPS documentation.
Signed-off-by: Pavel Machek <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
Acked-by: Chin Liang See <[email protected]>
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Enable initialization fo designware ethernet controller. With this
patch, ethernet works in my configuration, provided I set ethernet
address in the environment.
Signed-off-by: Pavel Machek <[email protected]>
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To fix the build error when build for Altera dev kit, not
virtual target. At same time, set the build for Altera dev
kit as default instead virtual target. With that, U-Boot
is booting well and SPL still lack of few drivers.
Signed-off-by: Chin Liang See <[email protected]>
Cc: Pavel Machek <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Albert Aribaud <[email protected]>
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Structure defining clock manager hardware was wrong, leading to
wrong registers being accessed and hang in MMC init.
This fixes structure to match hardware.
Signed-off-by: Pavel Machek <[email protected]>
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Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settings
Signed-off-by: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Wolfgang Denk <[email protected]>
CC: Pavel Machek <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Albert Aribaud <[email protected]>
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To enable the DesignWare watchdog support at SOCFPGA
Cyclone V dev kit.
Signed-off-by: Chin Liang See <[email protected]>
Cc: Anatolij Gustschin <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Heiko Schocher <[email protected]>
Cc: Tom Rini <[email protected]>
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Clock Manager driver will be called to reconfigure all the
clocks setting based on user input. The input are passed to
Preloader through handoff files
Signed-off-by: Chin Liang See <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
CC: Pavel Machek <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Acked-by: Pavel Machek <[email protected]>
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To add the DesignWare MMC driver support for Altera SOCFPGA. It
required information such as clocks and bus width from platform
specific files (SOCFPGA handoff files)
Signed-off-by: Chin Liang See <[email protected]>
Cc: Rajeshwari Shinde <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Cc: Pantelis Antoniou <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Acked-by: Pantelis Antoniou <[email protected]>
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Adding Freeze Controller driver. All HPS IOs need to be
in freeze state during pin mux or IO buffer configuration.
It is to avoid any glitch which might happen
during the configuration from propagating to external devices.
Signed-off-by: Chin Liang See <[email protected]>
Cc: Wolfgang Denk <[email protected]>
CC: Pavel Machek <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Albert Aribaud <[email protected]>
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Adding System Manager driver which will configure the
pin mux for real hardware Cyclone V development kit
(not Virtual Platform)
Signed-off-by: Chin Liang See <[email protected]>
Reviewed-by: Pavel Machek <[email protected]>
Acked-by: Dinh Nguyen <[email protected]>
Cc: Wolfgang Denk <[email protected]>
CC: Pavel Machek <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Albert Aribaud <[email protected]>
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Consolidating reset code into reset_manager.c. Also
separating reset configuration for virtual target and
real hardware Cyclone V development kit
Signed-off-by: Chin Liang See <[email protected]>
Reviewed-by: Pavel Machek <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Albert Aribaud <[email protected]>
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Signed-off-by: Wolfgang Denk <[email protected]>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <[email protected]>
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Add minimal support for Altera's SOCFPGA Cyclone 5 hardware.
Signed-off-by: Dinh Nguyen <[email protected]>
Signed-off-by: Chin Liang See <[email protected]>
Signed-off-by: Pavel Machek <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Acked-by: Tom Trini <[email protected]>
Cc: Wolfgang Denx <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Stefan Roese <[email protected]>
----
v8: Remove no_return attribute for reset_cpu
Based on v2012.10-rc2
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