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Consolidate HD headers and place the result into video/tegra20
since it is used only by devices from this directory.
Tested-by: Agneli <[email protected]> # Toshiba AC100 T20
Tested-by: Robert Eckelmann <[email protected]> # ASUS TF101
Tested-by: Andreas Westman Dorcsak <[email protected]> # ASUS Grouper E1565
Tested-by: Ion Agorria <[email protected]> # HTC One X
Tested-by: Svyatoslav Ryhel <[email protected]> # Nvidia Tegratab T114
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
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Diverge DC driver setup to better fit each of supported generations
of Tegra SOC.
Tested-by: Agneli <[email protected]> # Toshiba AC100 T20
Tested-by: Robert Eckelmann <[email protected]> # ASUS TF101
Tested-by: Andreas Westman Dorcsak <[email protected]> # ASUS Grouper E1565
Tested-by: Ion Agorria <[email protected]> # HTC One X
Tested-by: Svyatoslav Ryhel <[email protected]> # Nvidia Tegratab T114
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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This expansion is required for nonsecure detection to work correctly.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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TEGRA114_CLK_MIPI_CAL is a fixed child of PLLP and is used
as clock source of the MIPI PHY calibration mechanism.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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The existing pinctrl driver available for Tegra SOC is well
designed, but it lacks DM support. Let's add a DM compatible
overlay, which allows use of the device tree, along with preserving
backward compatibility with all existing setups and the ability
to use it in SPL board configuration stage.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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PLLD2 is a simple clock (controlled by 2 registers) and appears starting
from T30. Primary use of PLLD2 is as main HDMI clock parent.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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There's no need to replicate the pmu.h header file for every Tegra SoC
generation. Use a single header that is shared across generations.
Signed-off-by: Thierry Reding <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.
In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.
This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.
Signed-off-by: Tom Rini <[email protected]>
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In a number of places we had wordings of the GPL (or LGPL in a few
cases) license text that were split in such a way that it wasn't caught
previously. Convert all of these to the correct SPDX-License-Identifier
tag.
Signed-off-by: Tom Rini <[email protected]>
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Enabling a PLL while IDDQ is high. The Linux kernel checks for this
condition and warns about it verbosely, so while this seems to work
fine, fix it up according to the programming guidelines provided in
the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup
Sequence"). The Tegra114 TRM doesn't contain this information, but
the programming of PLLC is the same on Tegra114 and Tegra124.
Signed-off-by: Thierry Reding <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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On currently supported SoCs, clk_m always runs at the same frequency as
the oscillator input. However newer SoC generations such as Tegra210 no
longer have that restriction. Prepare for that by separating clk_m from
the oscillator clock and allow SoC code to override the clk_m rate.
Signed-off-by: Thierry Reding <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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arch/arm/cpu/arm720t/start.S includes <asm/arch/hardware.h>,
but the hardware.h headers of ARM720T boards are all empty.
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Linus Walleij <[email protected]>
Cc: Stephen Warren <[email protected]>
Cc: Tom Warren <[email protected]>
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Tegra210 starts its drive group registers at a different offset from the
APB MISC register block that other SoCs. Update the code to handle this.
Signed-off-by: Stephen Warren <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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On some future SoCs, some of the per-drive-group features no longer
exist. Add some ifdefs to support this.
Signed-off-by: Stephen Warren <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Future SoCs have a slightly different combination of pinmux options per
pin. This will be simpler to handle if we simply have one define per
option, rather than grouping various options together, in combinations
that don't align with future chips.
Signed-off-by: Stephen Warren <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Implement the powergate API that allows various power partitions to be
power up and down.
Signed-off-by: Thierry Reding <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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This converts the Tegra SPI drivers to use driver model. This is tested
on:
- Tegra20 - trimslice
- Tegra30 - beaver
- Tegra124 - dalmore
(not tested on Tegra124)
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
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On popular request this now completes the Warren's work started for
TK1:
aeb3fcb35956461077804720b8a252d50758d7e0
ARM: tegra: Use mem size from MC rather than ODMDATA
In addition to the move of using the Tegra memory controller (MC)
register rather than ODMDATA for T20, T30 and T114 as well it further
uses the generic get_ram_size() function (see "common/memsize.c")
<supposed to be used in each and every U-Boot port>TM. Added benefit is
that it should <catch 99% of hardware related (i. e. reliably
reproducible) memory errors> as well.
Thoroughly tested on the various Toradex line of Tegra modules
available which unfortunately does not include T114 and T124 (yet at
least) plus on the Jetson TK1.
Based-on-work-by: Stephen Warren <[email protected]>
Based-on-work-by: Tom Warren <[email protected]>
Signed-off-by: Marcel Ziswiler <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Becuase the board select menu in arch/arm/Kconfig is too big,
move the Tegra board select menu to tegra/Kconfig.
Insert the Tegra SoC select menu between the arch select and the
board select.
Architecture select
|-- Tegra Platform (Tegra)
|- Tegra SoC select (Tegra20 / 30 / 114 / 124)
|- Board select
Consolidate also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="tegra*") and always "select" CONFIG_SPL as follows:
config TEGRA
bool
select SPL
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Cc: Tom Warren <[email protected]>
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arch/arm/include/asm/spl.h requires all SoCs to have
arch/arm/include/asm/arch-*/spl.h.
But many of them just define BOOT_DEVICE_* macros.
Those macros are used in the "switch (boot_device) { ... }"
statement in common/spl/spl.c.
So they should not be archtecture specific, but be described as
a simpile enumeration.
This commit merges most of arch/arm/include/asm/arch-*/spl.h
into arch/arm/include/asm/spl.h.
With a little more effort, arch-zynq/spl.h and arch-socfpga/spl.h
will be merged, while I am not sure about OMAP and Exynos.
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Michal Simek <[email protected]>
Cc: Andreas Bießmann <[email protected]>
Cc: Stephen Warren <[email protected]>
Cc: Tom Warren <[email protected]>
CC: Stefano Babic <[email protected]>
CC: Minkyu Kang <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Acked-by: Andreas Bießmann <[email protected]>
Acked-by: Michal Simek <[email protected]>
Acked-by: Stefano Babic <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Acked-by: Tim Harvey <[email protected]>
Tested-by: Bo Shen <[email protected]> [on sama5d3xek board for at91 part]
Acked-by: Stephen Warren <[email protected]>
Tested-by: Stefano Babic <[email protected]> [applying Tim's i.MX6 patches]
Acked-by: Tom Rini <[email protected]>
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Define enum PMUX_FUNC_DEFAULT, which indicates that a table entry passed
to pinmux_config_pingrp()/pinmux_config_pingrp_table() shouldn't change
the mux option in HW.
For pins that will be used as GPIOs, the mux option is irrelevant, so we
simply don't want to define any mux option in the pinmux initialization
table.
Signed-off-by: Stephen Warren <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Use smaller fields in the Tegra pinmux structures in order to pack the
data tables into a smaller space. This saves around 1-3KB for the SPL
and around 3-8KB for the main build of U-Boot, depending on the board,
which SoC it uses, and how many pinmux table entries there are.
In order to pack PMUX_FUNC_* into a smaller space, don't hard-code the
values of PMUX_FUNC_RSVD* to values which require 16 bits to store them,
but instead let their values be assigned automatically, so they end up
fitting into 8 bits.
Signed-off-by: Stephen Warren <[email protected]>
Acked-by: Simon Glass <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Combine the Tegra USB header file into one header file for all SoCs.
Use ifdef to account for the difference, especially Tegra20 is quite
different from newer SoCs. This avoids duplication, mainly for
Tegra30 and newer devices.
Reviewed-by: Stephen Warren <[email protected]>
Signed-off-by: Stefan Agner <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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This renames all the pinmux pins, drive groups, and functions so they
have a prefix which matches the type name. These lists are also auto-
generated using scripts that were also used to generate the kernel
pinctrl drivers. This ensures that the lists are consistent between the
two.
The entries in tegra114_pingroups[] are all updated to remove the columns
which are no longer used.
All affected code is updated to match.
This introduces a few changes to pin/group/function naming and the set of
available functions for each pin. The new values now exactly match the
TRM; the chip documentation. I adjusted a few entries in
pinmux-config-dalmore.h due to this.
Signed-off-by: Stephen Warren <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Clean up the naming of pinmux-related objects:
* Refer to drive groups rather than pad groups to match the Linux kernel.
* Ensure all pinmux API types are prefixed with pmux_, values (defines)
are prefixed with PMUX_, and functions prefixed with pinmux_.
* Modify a few type names to make their content clearer.
* Minimal changes to SoC-specific .h/.c files are made so the code still
compiles. A separate per-SoC change will be made immediately following,
in order to keep individual patch size down.
Signed-off-by: Stephen Warren <[email protected]>
Acked-by: Simon Glass <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Much of arch/arm/cpu/tegra*-common/pinmux.c is identical. Remove the
duplication by creating pinmux-common.c for all the identical code.
This leaves:
* arch/arm/include/asm/arch-tegra*/pinmux.h defining only the names of
the various pins/pin groups, drive groups, and mux functions.
* arch/arm/cpu/tegra*-common/pinmux.c containing only the lookup table
stating which pin groups support which mux functions.
The code in pinmux-common.c is semantically identical to that in the
various original pinmux.c, but had some consistency and cleanup fixes
applied during migration.
I removed the definition of struct pmux_tri_ctlr, since this is different
between SoCs (especially Tegra20 vs all others), and it's much simpler to
deal with this via the new REG/MUX_REG/... defines. spl.c, warmboot.c,
and warmboot_avp.c needed updates due to this, since they previously
hijacked this struct to encode the location of some non-pinmux registers.
Now, that code simply calculates these register addresses directly using
simple and obvious math. I like this method better irrespective of the
pinmux code cleanup anyway.
Signed-off-by: Stephen Warren <[email protected]>
Acked-by: Simon Glass <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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pinmux_init() is a board-level function, not a pinmux driver function.
Move the prototype to a board header rather than the driver header.
Signed-off-by: Stephen Warren <[email protected]>
Acked-by: Simon Glass <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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This field isn't used anywhere, so remove it. Note that PIN() macros are
left unchanged for now, to avoid many diffs to them; later commits will
completely rewrite them just one time.
Signed-off-by: Stephen Warren <[email protected]>
Acked-by: Simon Glass <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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This field isn't used anywhere, so remove it. Note that PIN() macros are
left unchanged for now, to avoid many diffs to them; later commits will
completely rewrite them just one time.
Signed-off-by: Stephen Warren <[email protected]>
Acked-by: Simon Glass <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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<asm/arch-tegra/tegra.h> needs to use CONFIG_TEGRA* to conditionalize
some definitions, since some modules moved between generations. Move
the definition of CONFIG_TEGRAnn to a header that's included earlier,
so that it's set by the time tegra.h needs to use it.
Signed-off-by: Stephen Warren <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Tegra30 and Tegra114 are compatible except PLL parameters.
Tested on Tegra30 Cardhu, and Tegra114 Dalmore
platforms. All works well.
Signed-off-by: Jim Lin <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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T114 needs the SYSCTR0 counter initialized so the TSC can be
read by the kernel. Do it in the bootloader since it's a write-once
deal (secure/non-secure mode dependent).
Signed-off-by: Tom Warren <[email protected]>
Reviewed-by: Stephen Warren <[email protected]>
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SDIO1 (the SD-card slot on Dalmore) needs to have its pads setup
before the MMC driver is added.
Signed-off-by: Tom Warren <[email protected]>
Reviewed-by: Stephen Warren <[email protected]>
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Add driver for tegra114 SPI controller. This controller is not
compatible with either the tegra20 or tegra30 controllers, so it
requires a new driver.
Signed-off-by: Allen Martin <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
Reviewed-by: Stephen Warren <[email protected]>
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Pad config registers exist in APB_MISC_GP space, and control slew
rate, drive strengh, schmidt, high-speed, and low-power modes for
all of the pingroups in Tegra30. This builds off of the pinmux
way of constructing init tables to configure select pads (SDIOCFG,
for instance) during pinmux_init().
Currently, no padcfg entries exist. SDIO3CFG will be added when the
MMC driver is added as per the TRM to work with the SD-card slot on
Dalmore E1611.
Signed-off-by: Tom Warren <[email protected]>
Reviewed-by: Stephen Warren <[email protected]>
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Differences in padcfg registers (some removed, some added) between
Tegra30 and Tegra114 weren't picked up when I first ported this file.
Signed-off-by: Tom Warren <[email protected]>
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Use the latest tables & code from our internal U-Boot repo.
The SDMMC3_CD, CLK_LB_IN and CLK_LB_OUT offsets in the pingroup
table were off by a few indices, causing the pinmux init code to
write bad data to the PINMUX_AUX_ regs. This also enabled the lock
bit, which made it impossible to reconfig the pads correctly for
SDMMC3 (SD card on Dalmore) operation. Also fixes SPI_CS2_N,
USB_VBUS_EN0, HDMI_CEC and UART2_RXD/TXD muxes.
Signed-off-by: Tom Warren <[email protected]>
Reviewed-by: Stephen Warren <[email protected]>
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Common Tegra files are in arch-tegra, shared between T20/T30/T114.
Tegra114-specific headers are in arch-tegra114. Note that some of
these will be filled in as more T114 support is added (drivers,
WB/LP0 support, etc.).
Signed-off-by: Tom Warren <[email protected]>
Reviewed-by: Stephen Warren <[email protected]>
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