| Age | Commit message (Collapse) | Author |
|---|
|
When the data cache (dcache) is disabled, calling related
status functions can lead to compilation errors due to
undefined references.
Adding a !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) check before
invoking dcache_status() (used in common/memsize.c:get_ram_size())
and mmu_status() (from arch/arm/include/asm/io.h).
Without this check, builds with dcache disabled will fail to compile.
Signed-off-by: Boon Khai Ng <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
|
|
commit 2e2c2a5e72a8 ("arm: qemu: override flash accessors to use virtualizable instructions")
explains why we can't have instructions with multiple output registers
when running under QEMU + KVM and the instruction leads to an exception
to the hypervisor.
USB XHCI is such a case (MMIO) where a ldr w1, [x0], #4 is emitted for
xhci_start() which works fine with QEMU but crashes for QEMU + KVM.
These instructions cannot be emulated by KVM as they do not produce
syndrome information data that KVM can use to infer the destination
register, the faulting address, whether it was a load or store, or
if it's a 32 or 64 bit general-purpose register.
As a result an external abort is injected from QEMU, via ext_dabt_pending
to KVM and we end up throwing an exception that looks like
U-Boot 2025.07-rc4 (Jun 10 2025 - 12:00:15 +0000)
[...]
Register 8001040 NbrPorts 8
Starting the controller
"Synchronous Abort" handler, esr 0x96000010, far 0x10100040
elr: 000000000005b1c8 lr : 000000000005b1ac (reloc)
elr: 00000000476fc1c8 lr : 00000000476fc1ac
x0 : 0000000010100040 x1 : 0000000000000001
x2 : 0000000000000000 x3 : 0000000000003e80
x4 : 0000000000000000 x5 : 00000000477a5694
x6 : 0000000000000038 x7 : 000000004666f360
x8 : 0000000000000000 x9 : 00000000ffffffd8
x10: 000000000000000d x11: 0000000000000006
x12: 0000000046560a78 x13: 0000000046560dd0
x14: 00000000ffffffff x15: 000000004666eed2
x16: 00000000476ee2f0 x17: 0000000000000000
x18: 0000000046660dd0 x19: 000000004666f480
x20: 0000000000000000 x21: 0000000010100040
x22: 0000000010100000 x23: 0000000000000000
x24: 0000000000000000 x25: 0000000000000000
x26: 0000000000000000 x27: 0000000000000000
x28: 0000000000000000 x29: 000000004666f360
Code: d5033fbf aa1503e0 5287d003 52800002 (b8004401)
Resetting CPU ...
There are two problems making this the default.
- It will emit ldr + add or str + add instead of ldr/str(post increment)
in somne cases
- Some platforms that depend on TPL/SPL grow in size enough so that the
binary doesn't fit anymore.
So let's add proper I/O accessors add a Kconfig option
to turn it off by default apart from our QEMU builds.
Reported-by: Mikko Rapeli <[email protected]>
Tested-by: Mikko Rapeli <[email protected]>
Signed-off-by: Ilias Apalodimas <[email protected]>
|
|
asm/io.h is the header file containing the central MMIO accessor macros.
Judging by the header and the comments, it was apparently once copied
from the Linux kernel, but has deviated since then *heavily*. There is
absolutely no point in staying close to the original Linux code anymore,
so just remove the old cruft, by:
- removing pointless Linux history
- removing commented code
- removing outdated comments
- removing unused definitions (for mem_isa)
This massively improves the readability of the file.
Signed-off-by: Andre Przywara <[email protected]>
|
|
At early U-Boot stage, before relocation, MMU is not yet configured
and disabled. DDR may not be configured with the correct memory
attributes (can be configured in MT_DEVICE instead of MT_MEMORY).
In this case, usage of memcpy_{from, to}io() may leads to synchronous
abort in AARCH64 in case the normal memory address is not 64Bits aligned.
To avoid such situation, forbid usage of normal memory cast to (u64 *) in
case MMU is not enabled.
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
Cc: [email protected]
Signed-off-by: Patrick Delaunay <[email protected]>
|
|
Add 64bit API for clrbits and setbits.
Signed-off-by: Suneel Garapati <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
Port hypervisor related code from Mini-OS. This is referencing the code
of Mini-OS from [1] by Huang Shijie and Volodymyr Babchuk which is for
ARM64.
Update essential arch code to support required bit operations, memory
barriers etc.
Copyright for the bits ported belong to at least the following authors,
please see related files for details:
Copyright (c) 2002-2003, K A Fraser
Copyright (c) 2005, Grzegorz Milos, [email protected],Intel Research Cambridge
Copyright (c) 2014, Karim Allah Ahmed <[email protected]>
[1] - https://github.com/zyzii/mini-os.git
Signed-off-by: Oleksandr Andrushchenko <[email protected]>
Signed-off-by: Anastasiia Lukianenko <[email protected]>
[trini: Drop wmb() from musb-net/linux-compat.h now]
Signed-off-by: Tom Rini <[email protected]>
|
|
Provide optimized memcpy_{from,to}io() and memset_io(). This is required
when moving large amount of data to and from IO regions such as IP
registers or accessing memory mapped flashes.
Code is borrowed from Linux Kernel v5.4.
Signed-off-by: Vignesh Raghavendra <[email protected]>
Reviewed-by: Lokesh Vutla <[email protected]>
|
|
readb is unconditionally defined earlier in io.h, so there's no point
checking whether it's undefined.
Signed-off-by: Rasmus Villemoes <[email protected]>
|
|
No ARM board seems to define __mem_pci - and if it did, one would get tons of
./arch/arm/include/asm/io.h:307:0: warning: "readl" redefined
warnings, because readl and friends are unconditionally defined
earlier in io.h. Moreover, the redefinitions lack the memory barriers
that the first definitions have. So I'm guessing this is practically
dead code.
Signed-off-by: Rasmus Villemoes <[email protected]>
|
|
This patch port the function readX_relaxed and
writeX_relaxed from kernel 4.18.
Signed-off-by: Philippe Reynes <[email protected]>
|
|
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
|
|
Convert the arm architecture to make use of the new asm-generic/io.h to
provide address mapping functions. As the generic implementations are
suitable for arm this is primarily a matter of removing code.
This has only been build-tested, feedback from architecture maintainers
is welcome.
Signed-off-by: Paul Burton <[email protected]>
Cc: Albert Aribaud <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
As part of testing booting Linux kernels on Rockchip devices, it was
discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for
some cases incomplete isb definitions. This was causing a failure to
boot of the Linux kernel.
In order to solve this problem as well as cover any corner cases that we
may also have had a number of changes are made in order to consolidate
things. First, <asm/barriers.h> now becomes the source of isb/dsb/dmb
definitions. This however introduces another complexity. Due to
needing to build SPL for 32bit tegra with -march=armv4 we need to borrow
the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete
form. Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add
a comment about it. Now that we can always know what the target CPU is
capable off we can get always do the correct thing for the barrier. The
final part of this is that need to be consistent everywhere and call
isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the
function names in others.
Reviewed-by: Stephen Warren <[email protected]>
Tested-by: Stephen Warren <[email protected]>
Acked-by: Ziyuan Xu <[email protected]>
Acked-by: Sandy Patterson <[email protected]>
Reported-by: Ziyuan Xu <[email protected]>
Reported-by: Sandy Patterson <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
|
|
These defines are valid only when iomem_valid_addr is defined,
but I do not see such defines anywhere. Remove.
Signed-off-by: Masahiro Yamada <[email protected]>
|
|
ARM defines __raw_writes[bwql], __raw_reads[bwql] in arch io.h
but not the writes[bwql], reads[bwql] needed by some drivers.
Signed-off-by: Purna Chandra Mandal <[email protected]>
|
|
Data types and I/O functions have been defined for
64 bit physical addresses in arm.
Signed-off-by: Aneesh Bansal <[email protected]>
Reviewed-by: York Sun <[email protected]>
|
|
The QorIQ LS1 family is built on Layerscape architecture,
the industry's first software-aware, core-agnostic networking
architecture to offer unprecedented efficiency and scale.
Freescale LS102xA is a set of SoCs combines two ARM
Cortex-A7 cores that have been optimized for high
reliability and pack the highest level of integration
available for sub-3 W embedded communications processors
with Layerscape architecture and with a comprehensive
enablement model focused on ease of programmability.
Signed-off-by: Alison Wang <[email protected]>
Signed-off-by: Jason Jin <[email protected]>
Signed-off-by: Jingchang Lu <[email protected]>
Signed-off-by: Prabhakar Kushwaha <[email protected]>
|
|
When compiling u-boot with W=1 the extern inline void for
read* is likely causing the most noise. gcc / clang will
warn there is never a actual declaration for these functions.
Instead of declaring these extern make them static inline so
it is actually declared.
cc: Albert ARIBAUD <[email protected]>
Signed-off-by: Jeroen Hofstee <[email protected]>
|
|
Previously the driver was only tested on Power SoCs. Different barrier
instructions are needed for ARM SoCs.
Signed-off-by: York Sun <[email protected]>
|
|
This is needed for accessing peripherals with 64-bit MMIO registers,
from ARMv8 processors.
Signed-off-by: J. German Rivera <[email protected]>
|
|
Support the iotrace feature for ARM, when enabled.
Signed-off-by: Simon Glass <[email protected]>
|
|
Relocation code based on a patch by Scott Wood, which is:
Signed-off-by: Scott Wood <[email protected]>
Signed-off-by: David Feng <[email protected]>
|
|
Commit 3c0659b "ARM: Avoid compiler optimization for readb, writeb
and friends." introduced I/O accessors with memory barriers.
Unfortunately the new write*() accessors introduced a bug:
The problem is that the argument "v" gets evaluated twice. This
breaks code like used here (from "drivers/net/dnet.c"):
for (i = 0; i < wrsz; i++)
writel(*bufp++, &dnet->regs->TX_DATA_FIFO);
Use auxiliary variables to avoid such problems.
Signed-off-by: Wolfgang Denk <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Alexander Holler <[email protected]>
Cc: Dirk Behme <[email protected]>
|
|
gcc 4.5.1 seems to ignore (at least some) volatile definitions,
avoid that as done in the kernel.
Reading C99 6.7.3 8 and the comment 114) there, I think it is a bug of that
gcc version to ignore the volatile type qualifier used e.g. in __arch_getl().
Anyway, using a definition as in the kernel headers avoids such optimizations when
gcc 4.5.1 is used.
Maybe the headers as used in the current linux-kernel should be used,
but to avoid large changes, I've just added a small change to the current headers.
Signed-off-by: Alexander Holler <[email protected]>
Signed-off-by: Dirk Behme <[email protected]>
Signed-off-by: Wolfgang Denk <[email protected]>
Cc: Alessandro Rubini <[email protected]>
Tested-by: Thomas Weber <[email protected]>
Acked-by: Alexander Holler <[email protected]>
Tested-by: Alexander Holler <[email protected]>
|
|
These functions are undefined on ARM when using __io. These are the commonly
used versions and can be redefined.
Signed-off-by: Marek Vasut <[email protected]>
|
|
Signed-off-by: Terry Lv <[email protected]>
Fix commit message and code formatting.
Signed-off-by: Wolfgang Denk <[email protected]>
|
|
This helps to clean up the include/ directory so that it only contains
non-architecture-specific headers and also matches Linux's directory
layout which many U-Boot developers are already familiar with.
Signed-off-by: Peter Tyser <[email protected]>
|
