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Currently the M-mode trap handler codes are in start.S. For future
extension, move them to a separate file mtrap.S.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Lukas Auer <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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Currently start.S is inside arch/riscv/cpu/ax25/, but it can be
common for all RISC-V targets.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Lukas Auer <[email protected]>
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This adds a helper routine to print CPU information. Currently
it prints all the instruction set extensions that the processor
core supports.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Lukas Auer <[email protected]>
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