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Directly return the DDR size instead of the field of 'DxxxExxx'.
Move the function description to the header file.
Return 0 instead of 0xFF if read_eeprom() fails.
Reviewed-by: Heinrich Schuchardt <[email protected]>
Fixes: aea1bd95b61e ("eeprom: starfive: Enable ID EEPROM configuration")
Signed-off-by: Hal Feng <[email protected]>
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Don't imply non-existent symbols CONFIG_SIFIVE_CLINT and SPL_SIFIVE_CLINT.
MPFS boards neither use SPL nor do they run main U-Boot in M-mode.
So we don't need CONFIG_(SPL_)ACLINT either.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Acked-by: Conor Dooley <[email protected]>
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Tested on HiFive Unleashed and HiFive Unmatched, both SPIFlash and MMC boot.
Signed-off-by: Andreas Schwab <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Remove DECLARE_GLOBAL_DATA_PTR from files where gd is not used, and
drop the unnecessary inclusion of asm/global_data.h.
Headers should be included directly by the files that need them,
rather than indirectly via global_data.h.
Reviewed-by: Patrice Chotard <[email protected]> #STMicroelectronics boards and STM32MP1 ram test driver
Tested-by: Anshul Dalal <[email protected]> #TI boards
Acked-by: Yao Zi <[email protected]> #TH1520
Signed-off-by: Peng Fan <[email protected]>
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With commit 0535e46d55d7 ("scripts/dtc: Update to upstream version
v1.7.2-35-g52f07dcca47c") it is now a fatal error to U-Boot if our
device tree is not 8-byte aligned. In commit 85f586035d75 ("ARM: OMAP2+:
Pad SPL binary to 8-byte alignment before DTB") Beleswar Padhi explains
that we must have ALIGN(x) statements inside of a section to ensure that
padding is included and not simply that the linker address counter is
incremented. To that end, this patch:
- Aligns the final section before _end (for U-Boot) or _image_binary_end
(for xPL phases) by 8-bytes by adding '. = ALIGN(8);' to the final
section before the symbol.
- Remove a now-spurious '. = ALIGN(x);' statement that was intended to
provide the above alignments.
- Ensure that we do have alignment by adding an ASSERT so that when not
aligned we fail to link (and explain why).
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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There are multiple boards that use the PolarFire SoC, so extract
the Kconfig sections that are determined at a CPU level from the board
Kconfigs now that we have a CPU Kconfig.
Signed-off-by: Conor Dooley <[email protected]>
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PolarFire SoC needs a custom implementation of top_of_ram(), so stop
using the generic CPU & create a custom CPU instead.
Signed-off-by: Conor Dooley <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Add '\n' to the end of the warning message.
Besides, if we enable console record utility,
missing the '\n' causes the console_record_readline
fail to recognize the end of string.
Signed-off-by: Leo Yu-Chi Liang <[email protected]>
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This reverts commit a681cfecb4346107212f377e2075f6eb1bdc6a2b.
It has been reported that the commit causes boot regression for SPL on
StarFive VisionFive 2 or compatible boards. Inspecting the code, I did
spot one logic error for deciding whether Zaamo or Zalrsc is used, and
it's still unclear what exactly causes the regression, let's revert it
for now.
Reported-by: E Shattow <[email protected]>
Link: https://lore.kernel.org/u-boot/[email protected]/
Signed-off-by: Yao Zi <[email protected]>
Acked-by: E Shattow <[email protected]>
Acked-by: Leo Yu-Chi Liang <[email protected]>
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Add an alternative implementation that use Zalrsc extension only for
HART lottery and SMP locking to support SMP on cores without "Zaamo"
extension available. The Zaamo implementation is still prioritized if
both of them are available, since it takes fewer instructions.
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Imply OF_UPSTREAM in platform Kconfig option and adapt existing boards
to use the correct upstream devicetree paths.
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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ifdef CONFIG_CPU only works in U-Boot proper but macro is not working when
XPL phases are used. In this case CONFIG_SPL_CPU is also defined and can be
disabled which is causing compilation error.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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TH1520 SoC ships DMA peripherals that could only reach the first 32-bit
range of memory, for example, the GMAC controllers. Let's limit the
usable top of RAM below 4GiB to ensure DMA allocations are accessible to
all peripherals.
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Select PINCTRL_TH1520 in CPU Kconfig entry and update defconfig for
existing TH1520-based boards to ensure PINCTRL is enabled.
Signed-off-by: Yao Zi <[email protected]>
Acked-by: Leo Yu-Chi Liang <[email protected]>
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On coldboot, only HART 0 among the four HARTs of TH1520 is brought up by
hardware, and the remaining HARTs are in reset states, requiring manual
setup of reset address and deassertion to function normal. Introduce a
routine to do the work.
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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C910 cores integrated in TH1520 SoC provide various customized CSRs for
configuring core behavior, including cache coherency and timing, branch
predication, and clock gating for internal components.
This patch sets them up for efficient operation and satisfying
requirements of an SMP system.
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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These operations rely on a customized M-mode CSR, MHCR, which isn't
available when running in S mode.
Let's fallback to the generic weak stub when running in S mode to avoid
illegal accesses.
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Symbols in spl.c only function correctly in SPL stage. Build the file
for SPL only to avoid weak symbols in proper U-Boot being unexpectedly
reloaded.
Fixes: 5fe9ced3552 ("riscv: cpu: Add TH1520 CPU support")
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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The clock driver is essential for TH1520 SoCs to operate. Select the
driver in SoC Kconfig entry.
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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TH1520 SoC ships several IOPMPs protecting various on-chip peripherals.
They must be configured before accessing the peripherals. Let's
initialize them in SPL harts_early_init().
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Introduce the SoC-specific code and corresponding Kconfig entries for
TH1520 SoC. Following features are implemented for TH1520,
- Cache enable/disable through customized CSR
- Invalidation of customized PMP entries
- DRAM driver probing for SPL
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Designed before a standard set of cache management operations defined in
RISC-V, earlier T-Head cores like C906 and C910 provide CMO through the
customized extension XTheadCMO, which has been used in the CV1800B port
of U-Boot.
This patch splits XTheadCMO-related code into a generic module, allowing
SoCs shipping T-Head cores to share the code.
Link: https://github.com/XUANTIE-RV/thead-extension-spec
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Similar to AArch64's case, Clang may wrongly fold accesses to gd pointer
which is defined with register qualifier into constants, breaking
various components.
This patch defines gd as a macro when building with Clang or LTO, which
expands to get_gd() that accesses gp pointer in assembly, making RISC-V
ports function properly and preparing for introduction of LTO in the
future. Board initialization code is also adapted for non-assignable gd.
Reported-by: Nathaniel Hourt <[email protected]>
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Binman looks for __image_copy_start to determine the base address of an
entry if elf-base-sym isn't specified, which is missing in RISC-V port.
This causes binman skips RISC-V SPL entries without filling addresses
into its .binman_sym_table section.
This patch defines __image_copy_start in linkerscript of both SPL and
proper U-Boot to ensure binman_sym functions correctly with the default
binman.dtsi. The paired symbol, __image_copy_end, is introduced as well
for completeness.
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add RESET_SPACEMIT_K1 option in config.
Signed-off-by: Huan Zhou <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Now that we have the same option for SPL and TPL, simplify the logic for
determining the initial stack.
Note that this changes behaviour as current SPL_STACK is a fallback for
TPL. However, that was likely unintended and can be handled with Kconfig
defaults if needed.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Suggested-by: Tom Rini <[email protected]>
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At present there is a hex value SPL_STACK which both determines whether
SPL has its own initial stack and the hex value of that stack.
Split off the former into SPL_HAVE_INIT_STACK with SPL_STACK depending
on that and only providing the latter.
Signed-off-by: Simon Glass <[email protected]>
[trini: Resync defconfig files]
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JH7110 SoC requires no specific handling before entering Linux kernel.
Let's drop the specific implementation to avoid duplication.
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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The current implementation is equivalent to the fallback one, so
this shouldn't change any behaviour but cleans the code up only.
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Most RISC-V SoCs have similar cleanup_before_linux() functions. Let's
provide a weak symbol as fallback to reduce duplicated code.
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Implement functionality to probe and calculate the DRAM size
during the boot phase for the RISC-V spacemit K1 platform.
Tested-by: Marcel Ziswiler <[email protected]> # BPI-F3 16G
Signed-off-by: Huan Zhou <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Add Canaan K230 SoC with sysreset support, running without cache
enabled.
Signed-off-by: Junhui Liu <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Update the cpu probing to fallback to "riscv,isa" property if
"riscv,isa-extensions" is not available and modify the riscv CMO code
to use the block size that was probed during cpu setup.
Signed-off-by: Mayuresh Chitale <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Enhance the existing extension probing mechanism by adding support for
more extensions and probing using the "riscv,isa" property. This patch
is ported from the latest upstream linux.
Signed-off-by: Mayuresh Chitale <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Add basic support for SpacemiT's Banana Pi F3 board.
Update the k1.dtsi align with mainline.
Note that the device tree files follow the mainline Linux source[1].
Links: https://patches.linaro.org/project/linux-serial/patch/[email protected]/ [1]
Signed-off-by: Kongyang Liu <[email protected]>
Signed-off-by: Huan Zhou <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
Reviewed-by: Yixun Lan <[email protected]>
Tested-by: Marcel Ziswiler <[email protected]>
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The imply statements should be sorted in the sequence
of appearance in .config.
Tested-by: Anand Moon <[email protected]>
Tested-by: E Shattow <[email protected]>
Suggested-by: Heinrich Schuchardt <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
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Enable OF_UPSTREAM to use upstream DT and add starfive/ prefix to
the DEFAULT_DEVICE_TREE. Rename jh7110-starfive-visionfive-2-u-boot.dtsi
to jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi and set the v1.3b
device tree as the default device tree.
Drop redundant DT files from arch/riscv/dts/ and redundant clock and
reset definitions from include/dt-bindings/.
Since the old clock definitions is a little different from those in
upstream Linux, update the clock definitions in clock drivers
accordingly.
Tested-by: Anand Moon <[email protected]>
Tested-by: E Shattow <[email protected]>
Acked-by: Sumit Garg <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
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Use the new symbol to refer to any 'SPL' build, including TPL and VPL
Signed-off-by: Simon Glass <[email protected]>
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AST2700 SoCs integrates a Ibex 32-bits RISC-V core as the boot MCU
for the first stage bootloader execution, namely SPL.
This patch implements the preliminary base to successfully run SPL
on this RV32-based MCU to the console banner message.
Signed-off-by: Chia-Wei Wang <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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The _image_binary_end symbol was aligned to the 8-bytes boundary.
However, the SPL device tree (u-boot-spl.dtb) is concatenated right
after the binary (u-boot-spl-nodtb.bin) wihtout the consideration of
the 8-bytes alignment restriction.
After then, for the SPL_SEPARATE_BSS case, fdtdec_setup() searching
for the DTB by _image_binary_end will return the "Missing DTB" error.
As the real DTB starting point does not align to a 8-bytes address
like _image_binary_end does.
Signed-off-by: Chia-Wei Wang <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Use CSR_UCCTLCOMMAND instead of CSR_MCCTLCOMMAND
to do cache flush operation in M-mode and S-mode.
Signed-off-by: Leo Yu-Chi Liang <[email protected]>
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Cache could be enabled in harts_early_init board-specific hook,
so remove cache enablement in start.S
Signed-off-by: Leo Yu-Chi Liang <[email protected]>
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Signed-off-by: Leo Yu-Chi Liang <[email protected]>
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Rename spl_soc_init() to spl_dram_init() because the generic function
name does not reflect what the function actually does. Also
spl_dram_init() is commonly used for dram initialization and should be
called from board_init_f().
Signed-off-by: Lukas Funke <[email protected]>
Reviewed-by: Heinrich Schuchardt <[email protected]>
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Rename spl_soc_init() to spl_dram_init() because the generic function
name does not reflect what the function actually does. Also
spl_dram_init() is commonly used for dram initialization and should be
called from board_init_f().
Signed-off-by: Lukas Funke <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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The instruction and data cache line sizes of Andes core
are 64-byte. Select SYS_CACHE_SHIFT_6 for RISCV_NDS so
the SYS_CACHELINE_SIZE is enabled with a default value.
Signed-off-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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A new property has been added, with an extensive rationale at [1], that
can be used in place of "riscv,isa" to indicate what extensions are
supported by a given platform that is a list of strings rather than a
single string. There are some differences between the new property,
"riscv,isa-extensions" and the incumbent "riscv,isa" - chief among them
for the sake of parsing being the list of strings, as opposed to a
string. Another advantage is strictly defined meanings for each string
in a dt-binding, rather than deriving meaning from RVI standards. This
will likely to some divergence over time, but U-Boot's current use of
extension detection is very limited - there are just four callsites of
supports_extension() in mainline U-Boot.
These checks are limited to two checks for FPU support and two checks
for "s" and "u". "s" and "u" are not supported by the new property, but
they were also not permitted in "riscv,isa". These checks are only
meaningful (or run) in M-Mode, in which case supports_extension() does
not parse the devicetree anyway.
Add support for the new property in U-Boot, prioritising it, before
falling back to the, now deprecated, "riscv,isa" property if it is not
present.
Signed-off-by: Conor Dooley <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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cpu_get_desc() for the RISC-V CPU currently reads "riscv,isa" to get
the description, but it is no longer a required property and cannot be
assummed to always be present, as the new "riscv,isa-extensions" and
"riscv,isa-base" properties may be present instead.
On RISC-V, cpu_get_desc() has two main uses - firstly providing an
informational name for the CPU for smbios or at boot with
DISPLAY_CPUINFO etc and secondly it forms the basis of ISA extension
detection in supports_extension() as it returns (a portion of) an ISA
string.
cpu_get_desc() returns a string, which aligned with "riscv,isa" but
the new property is a list of strings. Rather than add support for
the list of strings property, which would require creating an isa
string from "riscv,isa-extensions", modify the RISC-V CPU's
implementaion of cpu_get_desc() return the first compatible as the
cpu description instead. This may be fine for the informational cases,
but it would break extension dtection, given supports_extension()
expects cpu_get_desc() to return an ISA string.
Call dev_read_string() directly in supports_extension() to get the
contents of "riscv,isa" so that extension detection remains functional.
As a knock-on affect of this change, extension detection is no longer
broken for long ISA strings. Previously if the ISA string exceeded the
32 element array that supports_extension() passed to cpu_get_desc(),
it would return ENOSPC and no extensions would be detected.
This bug probably had no impact as U-Boot does not currently do anything
meaningful with the results of supports_extension() and most SoCs
supported by U-Boot don't have anywhere near that complex of an ISA
string. The QEMU virt machine's CPUs do however, so extension detection
doesn't work there.
Signed-off-by: Conor Dooley <[email protected]>
reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Add dcache operations invalidate_dcache_range and flush_dcache_range for
cv1800b.
Signed-off-by: Kongyang Liu <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Add Sophgo cv1800b SoC to support RISC-V arch.
Signed-off-by: Kongyang Liu <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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