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Age	Commit message (Expand)	Author
2023-02-17	riscv: Rename Andes cpu and board names	Leo Yu-Chi Liang
2023-02-17	configs: ae350: Enable v5l2 cache for AE350 platforms in SPL	Yu Chien Peter Lin
2023-02-17	riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL	Yu Chien Peter Lin
2023-02-17	riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()	Yu Chien Peter Lin
2023-02-17	riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"	Leo Yu-Chi Liang
2023-02-01	riscv: ax25: bypass malloc when spl fit boots from ram	Rick Chen
2023-02-01	riscv: ae350: Enable CCTL_SUEN	Rick Chen
2022-11-03	riscv: Rename Andes PLIC to PLICSW	Yu Chien Peter Lin
2021-10-07	riscv: ae350: enable Coherence Manager for ae350	Leo Yu-Chi Liang
2021-03-27	cpu: Rename SPL_CPU_SUPPORT to SPL_CPU	Simon Glass
2020-10-26	timer: Add _TIMER suffix to Andes PLMT Kconfig	Sean Anderson
2020-09-30	riscv: Rework riscv timer driver to only support S-mode	Sean Anderson
2020-05-18	common: Drop net.h from common header	Simon Glass
2020-04-23	riscv: ax25: cache: Remove SPL_RISCV_MMODE config check	Pragnesh Patel
2019-12-10	riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL	Rick Chen
2019-12-10	riscv: ax25: add SPL support	Rick Chen
2019-12-02	common: Move ARM cache operations out of common.h	Simon Glass
2019-12-02	common: Move some cache and MMU functions out of common.h	Simon Glass
2019-09-03	riscv: cache: use CCTL to flush d-cache	Rick Chen
2019-09-03	riscv: cache: Flush L2 cache before jump to linux	Rick Chen
2019-09-03	riscv: ax25: add imply v5l2 cache controller	Rick Chen
2019-08-26	riscv: add run mode configuration for SPL	Lukas Auer
2019-05-18	CONFIG_SPL_SYS_[DI]CACHE_OFF: add	Trevor Woerner
2019-04-08	riscv: ax25: Andes specific cache shall only support in M-mode	Rick Chen
2019-04-08	riscv: ax25: Add platform-specific Kconfig options	Rick Chen
2019-01-15	riscv: move the AX25-specific implementation of flush_dcache_all	Lukas Auer
2018-12-18	riscv: ax25: Hide the ax25-specific Kconfig option	Bin Meng
2018-11-26	riscv: cache: Implement i/dcache [status, enable, disable]	Rick Chen
2018-10-03	riscv: Move do_reset() to a common place	Bin Meng
2018-10-03	riscv: Make start.S available for all targets	Bin Meng
2018-10-03	riscv: Move the linker script to the CPU root directory	Bin Meng
2018-08-20	riscv: Include bss subsections in linker script	Alexander Graf
2018-07-25	efi_loader: Rename sections to allow for implicit data	Alexander Graf
2018-05-29	riscv: cpu: nx25: Rename as ax25	Rick Chen