| Age | Commit message (Collapse) | Author |
|---|
|
The current ae350-related defconfigs could also
support newer Andes CPU IP, so modify the names of CPU
from ax25 to andesv5, and board name from ax25-ae350 to ae350.
Signed-off-by: Leo Yu-Chi Liang <[email protected]>
Reviewed-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
|
|
To reduce the code size, CONFIG_V5L2_CACHE was disabled since commit:
ca06444aac2c643db3a3f2eb37afc60fae15177e
Turing on does not significantly increase the size of u-boot-spl.bin,
so we enable it by default to improve performance.
Signed-off-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
|
|
This patch refines L1 cache enable/disable and v5l2-cache enable
functions.
Signed-off-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
|
|
As the OpenSBI v1.2 does not enable the cache [0], we enable
the i/d-cache in harts_early_init() and do not disable in
cleanup_before_linux(). This patch also simplifies the logic
and moves the CSR encoding to include/asm/arch-andes/csr.h.
[0] https://github.com/riscv-software-src/opensbi/commit/bd7ef4139829da5c30fa980f7498d385124408fa
Signed-off-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
|
|
There is no need for RISCV_NDS_CACHE config to control cache switches.
Signed-off-by: Leo Yu-Chi Liang <[email protected]>
Reviewed-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
|
|
When fit image boots from ram, the payload will
be prepared in the address of SPL_LOAD_FIT_ADDRESS.
In spl fit generic flow, it will malloc another
memory address and copy whole fit image to this
malloc address. But it is un-necessary for booting
from RAM.
This patch improves this flow by declare the
board_spl_fit_buffer_addr() to replace the original one.
The larger image size (eq: Kernel Image 10~20MB), it
can save more booting time.
Signed-off-by: Rick Chen <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
|
|
CCTL operations are available to Supervisor/User-mode
software under the control of the mcache_ctl.CCTL_SUEN
control bit. Enable it to support Supervisor(and User)
CCTL operations.
Signed-off-by: Rick Chen <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
|
|
As PLICSW is used to trigger the software interrupt, we should rename
Andes PLIC configuration and file name to reflect the usage. This patch
also updates PLMT and PLICSW compatible strings to be consistent with
OpenSBI fdt driver.
Signed-off-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
|
|
If Coherence Manager were not set in the beginning,
u-boot-spl would sometimes fail to boot to u-boot proper.
Enable CM and I/D cache at the same time in harts_early_init
Signed-off-by: Leo Yu-Chi Liang <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
|
|
The _SUPPORT suffix is from an earlier time and interferes with use of
the CONFIG_IS_ENABLED() macro. Rename the option to drop the suffix.
Tidy up the TODO that prompted this.
Signed-off-by: Simon Glass <[email protected]>
|
|
This matches the naming scheme of other timer drivers.
Signed-off-by: Sean Anderson <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
|
|
The riscv-timer driver currently serves as a shim for several riscv timer
drivers. This is not too desirable because it bypasses the usual timer
selection via the driver model. There is no easy way to specify an
alternate timing driver, or have the tick rate depend on the cpu's
configured frequency. The timer drivers also do not have device structs,
and so have to rely on storing parameters in gd_t. Lastly, there is no
initialization call, so driver init is done in the same function which
reads the time. This can result in confusing error messages. To a user, it
looks like the driver failed when trying to read the time, whereas it may
have failed while initializing.
This patch removes the shim functionality from the riscv-timer driver, and
has it instead implement the former rdtime.c timer driver. This is because
existing u-boot users who pass in a device tree (e.g. qemu) do not create a
timer device for S-mode u-boot. The existing behavior of creating the
riscv-timer device in the riscv cpu driver must be kept. The actual reading
of the CSRs has been redone in the style of Linux's get_cycles64.
Signed-off-by: Sean Anderson <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
|
|
Move this header out of the common header. Network support is used in
quite a few places but it still does not warrant blanket inclusion.
Note that this net.h header itself has quite a lot in it. It could be
split into the driver-mode support, functions, structures, checksumming,
etc.
Signed-off-by: Simon Glass <[email protected]>
|
|
CONFIG_IS_ENABLED(FOO) will check FOO config option for U-Boot,
SPL and TPL, so remove unnecessary CONFIG_IS_ENABLED()
Signed-off-by: Pragnesh Patel <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
|
|
The mcache_ctl csr only can be manipulated in M mode.
Add SPL_RISCV_MMODE for U-Boot SPL to control cache
operation.
Signed-off-by: Rick Chen <[email protected]>
Cc: KC Lin <[email protected]>
Cc: Alan Kao <[email protected]>
|
|
The U-Boot SPL will boot in M mode and load the FIT image which
include OpenSBI and U-Boot proper images. After loading progress,
it will jump to OpenSBI first and then U-Boot proper which will
run in S mode.
Also remove V5L2_CACHE due to U-Boot SPL code size consideration.
Without this concern, it can be enable manually for performance.
Signed-off-by: Rick Chen <[email protected]>
Cc: KC Lin <[email protected]>
Cc: Alan Kao <[email protected]>
|
|
These functions are CPU-related and do not use driver model. Move them to
cpu_func.h
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
|
|
These functions belong in cpu_func.h. Another option would be cache.h
but that code uses driver model and we have not moved these cache
functions to use driver model. Since they are CPU-related it seems
reasonable to put them here.
Move them over.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
|
|
Use CCTL command to do d-cache write back
and invalidate instead of fence.
Signed-off-by: Rick Chen <[email protected]>
Cc: KC Lin <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
|
|
Flush and disable L2 cache in dcache_disable()
which will be called in cleanup_before_linux()
before jump to linux.
The sequence will be preferred as below:
L1 flush -> L1 disable -> L2 flush -> L2 disable
Signed-off-by: Rick Chen <[email protected]>
Cc: KC Lin <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
|
|
Select the v5l2 UCLASS_CACHE driver for ax25.
Signed-off-by: Rick Chen <[email protected]>
Cc: KC Lin <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
|
|
U-Boot SPL can be run in a different privilege mode from U-Boot proper.
Add new configuration entries for SPL to allow the run mode to be
configured independently of U-Boot proper.
Extend all uses of the CONFIG_RISCV_SMODE and CONFIG_RISCV_MMODE
configuration symbols to also cover the SPL equivalents. Ensure that
files compatible with only one privilege mode are not included in builds
targeting an incompatible privilege mode.
Signed-off-by: Lukas Auer <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Tested-by: Bin Meng <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances
where these configuration items are conditional on SPL. This commit adds SPL
variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates
the configurations as required.
Acked-by: Alexey Brodkin <[email protected]>
Signed-off-by: Trevor Woerner <[email protected]>
[trini: Make the default depend on the setting for full U-Boot, update
more zynq hardware]
Signed-off-by: Tom Rini <[email protected]>
|
|
Limit the cache configuration only can be supported in M mode.
It can not be manipulated in S mode.
Signed-off-by: Rick Chen <[email protected]>
Cc: Greentime Hu <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Lukas Auer <[email protected]>
|
|
Add ax25 RISC-V platform-specific Kconfig options,
to include CPU and timer drivers. Also disable
ATCPIT100 SoC timer and replace by PLMT.
Signed-off-by: Rick Chen <[email protected]>
Cc: Greentime Hu <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Lukas Auer <[email protected]>
|
|
The fence instruction is used to enforce device I/O and memory ordering
constraints in RISC-V. It can not be relied on to directly affect the
data cache on every CPU.
Andes' AX25 does not have a coherence agent. Its fence instruction
flushes the data cache and is used to keep data in the system coherent.
The implementation of flush_dcache_all in lib/cache.c is therefore
specific to the AX25. Move it into the AX25-specific cache.c in
cpu/ax25/.
This also adds a missing new line between flush_dcache_all and
flush_dcache_range in lib/cache.c.
Signed-off-by: Lukas Auer <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
|
|
There is no need to expose RISCV_NDS to the Kconfig menu as it is
an ax25-specific option. Introduce a dedicated Kconfig option for
the cache ops of ax25 platform and use that to guard the cache ops.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Lukas Auer <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
|
|
AndeStar RISC-V(V5) provide mcache_ctl register which
can configure I/D cache as enabled or disabled.
This CSR will be encapsulated by CONFIG_RISCV_NDS.
If you want to configure cache on AndeStar V5
AE350 platform. YOu can enable [*] AndeStar V5 ISA support
by make menuconfig.
This approach also provide the expansion when the
vender specific features are going to join in.
Signed-off-by: Rick Chen <[email protected]>
Cc: Greentime Hu <[email protected]>
|
|
We don't have a reset method on any RISC-V board yet. Instead of
adding the same 'unsupported' message for each CPU variant it might
make more sense to add a generic do_reset function for all CPU
variants to lib/, similar to the one for ARM (arch/arm/lib/reset.c).
Suggested-by: Lukas Auer <[email protected]>
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Lukas Auer <[email protected]>
|
|
Currently start.S is inside arch/riscv/cpu/ax25/, but it can be
common for all RISC-V targets.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Lukas Auer <[email protected]>
|
|
The linker script can be shared by all RISC-V targets. Move it to
a common place.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Lukas Auer <[email protected]>
|
|
When we build with -fdata-sections we may end up with bss subsections. Our
linker script explicitly lists only a single consecutive bss section though.
Adapt the statement to also include subsections.
Signed-off-by: Alexander Graf <[email protected]>
|
|
Some times gcc may generate data that is then used within code that may
be part of an efi runtime section. That data could be jump tables,
constants or strings.
In order to make sure we catch these, we need to ensure that gcc emits
them into a section that we can relocate together with all the other
efi runtime bits. This only works if the -ffunction-sections and
-fdata-sections flags are passed and the efi runtime functions are
in a section that starts with ".text".
Up to now we had all efi runtime bits in sections that did not
interfere with the normal section naming scheme, but this forces
us to do so. Hence we need to move the efi_loader text/data/rodata
sections before the global *(.text*) catch-all section.
With this patch in place, we should hopefully have an easier time
to extend the efi runtime functionality in the future.
Signed-off-by: Alexander Graf <[email protected]>
[agraf: Fix x86_64 breakage]
|
|
Andes has rearranged the product combinations.
nx25 and ax25 both are RISC-V architecture cpu core.
But ax25 has MMU unit inside, and nx25 is not.
Cpu nx25 and platform ae250 are arranged in pairs.
Cpu ax25 and platform ae350 are arranged in pairs.
This patch will rename
nx25 as ax25
ae250 as ae350
nx25-ae250 as ax25-ae350
including filename, variable, string and definition.
Then u-boot can boot linux kernel in ae350
platform reasonably.
Signed-off-by: Rick Chen <[email protected]>
Signed-off-by: Rick Chen <[email protected]>
Cc: Greentime Hu <[email protected]>
|
