| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2024-10-11 | arch: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD | Simon Glass | |
| Use the new symbol to refer to any 'SPL' build, including TPL and VPL Signed-off-by: Simon Glass <[email protected]> | |||
| 2021-09-07 | board: sifive: use ccache driver instead of helper function | Zong Li | |
| Invokes the common cache_init function to initialize ccache. Signed-off-by: Zong Li <[email protected]> Reviewed-by: Sean Anderson <[email protected]> Reviewed-by: Rick Chen <[email protected]> | |||
| 2020-07-03 | riscv: sifive: fu540: enable all cache ways from U-Boot proper | Pragnesh Patel | |
| Add L2 cache node to enable all cache ways from U-Boot proper. Signed-off-by: Pragnesh Patel <[email protected]> Reviewed-by: Bin Meng <[email protected]> Tested-by: Bin Meng <[email protected]> | |||
| 2020-06-04 | riscv: sifive: fu540: add SPL configuration | Pragnesh Patel | |
| Add a support for SPL which will boot from L2 LIM (0x0800_0000) and then SPL will boot U-Boot FIT image (OpenSBI FW_DYNAMIC + u-boot.bin) from MMC boot devices. SPL related code is leveraged from FSBL (https://github.com/sifive/freedom-u540-c000-bootloader.git) Signed-off-by: Pragnesh Patel <[email protected]> Reviewed-by: Bin Meng <[email protected]> Tested-by: Bin Meng <[email protected]> Reviewed-by: Jagan Teki <[email protected]> Tested-by: Jagan Teki <[email protected]> | |||
| 2020-06-04 | riscv: cpu: fu540: Add support for cpu fu540 | Pragnesh Patel | |
| Add SiFive fu540 cpu to support RISC-V arch Signed-off-by: Pragnesh Patel <[email protected]> Reviewed-by: Bin Meng <[email protected]> Tested-by: Bin Meng <[email protected]> Reviewed-by: Jagan Teki <[email protected]> Tested-by: Jagan Teki <[email protected]> | |||
