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2026-03-13sifive: switch to OF_UPSTREAMAndreas Schwab
Tested on HiFive Unleashed and HiFive Unmatched, both SPIFlash and MMC boot. Signed-off-by: Andreas Schwab <[email protected]> Reviewed-by: Leo Yu-Chi Liang <[email protected]>
2024-10-11arch: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILDSimon Glass
Use the new symbol to refer to any 'SPL' build, including TPL and VPL Signed-off-by: Simon Glass <[email protected]>
2024-05-02board: sifive: Rename spl_soc_init() to spl_dram_init()Lukas Funke
Rename spl_soc_init() to spl_dram_init() because the generic function name does not reflect what the function actually does. Also spl_dram_init() is commonly used for dram initialization and should be called from board_init_f(). Signed-off-by: Lukas Funke <[email protected]> Reviewed-by: Leo Yu-Chi Liang <[email protected]>
2023-10-24riscv: Remove common.h usageTom Rini
We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <[email protected]> Reviewed-by: Rick Chen <[email protected]>
2023-08-15common: return type board_get_usable_ram_topHeinrich Schuchardt
board_get_usable_ram_top() returns a physical address that is stored in gd->ram_top. The return type of the function should be phys_addr_t like the current type of gd->ram_top. Signed-off-by: Heinrich Schuchardt <[email protected]>
2023-07-12riscv: Rename SiFive CLINT to RISC-V ALINTBin Meng
As the RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V ALINT in the source tree to be future-proof. Signed-off-by: Bin Meng <[email protected]> Reviewed-by: Rick Chen <[email protected]>
2022-09-23board_f: Fix types for board_get_usable_ram_top()Pali Rohár
Commit 37dc958947ed ("global_data.h: Change ram_top type to phys_addr_t") changed type of ram_top member from ulong to phys_addr_t but did not changed types in board_get_usable_ram_top() function which returns value for ram_top. So change ulong to phys_addr_t type also in board_get_usable_ram_top() signature and implementations. Fixes: 37dc958947ed ("global_data.h: Change ram_top type to phys_addr_t") Signed-off-by: Pali Rohár <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2021-12-02riscv: Enable SPI flash env for SiFive Unmatched.Thomas Skibo
Enable saving environment to SPI flash memory on SiFive Unmatched. Signed-off-by: Thomas Skibo <[email protected]> Reviewed-by: Leo Yu-Chi Liang <[email protected]>
2021-09-07board: sifive: use ccache driver instead of helper functionZong Li
Invokes the common cache_init function to initialize ccache. Signed-off-by: Zong Li <[email protected]> Reviewed-by: Sean Anderson <[email protected]> Reviewed-by: Rick Chen <[email protected]>
2021-08-17riscv: cpu: fu740: Fix typo of dateZong Li
Fixed the typo of date of copyright declaration. Signed-off-by: Zong Li <[email protected]> Reviewed-by: Bin Meng <[email protected]>
2021-07-28i2c: Rename SPL/TPL_I2C_SUPPORT to I2CSimon Glass
Rename these options so that CONFIG_IS_ENABLED can be used with them. Signed-off-by: Simon Glass <[email protected]> Reviewed-by: Heiko Schocher <[email protected]>
2021-07-06riscv: sifive: fu740: Support i2c in splZong Li
Enable SPL_I2C_SUPPORT for fu740, and add 'u-boot,dm-spl' property in i2c node. Signed-off-by: Zong Li <[email protected]> Reviewed-by: Leo Yu-Chi Liang <[email protected]>
2021-07-06riscv: sifive: fu740: kconfig: Enable support for Opencores I2C controllerZong Li
Enable the Opencores I2C controller on FU740 Signed-off-by: Zong Li <[email protected]> Reviewed-by: Leo Yu-Chi Liang <[email protected]>
2021-05-31riscv: cpu: fu740: clear feature disable CSRGreen Wan
Clear feature disable CSR to turn on all features of hart. The detail is specified at section, 'SiFive Feature Disable CSR', in user manual https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdf Signed-off-by: Green Wan <[email protected]> Reviewed-by: Sean Anderson <[email protected]> Reviewed-by: Bin Meng <[email protected]> Reviewed-by: Rick Chen <[email protected]>
2021-05-31riscv: cpu: fu740: Add support for cpu fu740Green Wan
Add SiFive fu740 cpu to support RISC-V arch Signed-off-by: Green Wan <[email protected]> Reviewed-by: Bin Meng <[email protected]>