| Age | Commit message (Collapse) | Author |
|---|
|
The U_BOOT_DRIVER macro creates a list of drivers used at link time, and
all entries here must be unique. This in turn means that all entries in
the code should also be unique in order to not lead to build failures
later with unexpected build combinations. Typically, the problem we have
here is when a driver is obviously based on another driver and didn't
update this particular field and so while the name field reflects
something unique the linker entry itself is not. In a few places this
provides a more suitable string name as well, however.
Reviewed-by: Marek Vasut <[email protected]>
Reviewed-by: Svyatoslav Ryhel <[email protected]> # Tegra
Reviewed-by: Peter Robinson <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
|
|
A few clock drivers cannot build without access to some platform
specific header files. Express those requirements in Kconfig as well.
Signed-off-by: Tom Rini <[email protected]>
|
|
Remove default values for PMC PLL Analog Control Register(ACR) as the
values are specific for each SoC and PLL, so load them from PLL
characteristics structure
Signed-off-by: Manikandan Muralidharan <[email protected]>
Signed-off-by: Varshini Rajendran <[email protected]>
|
|
Add ACR in all PLL setting. Add correct ACR value for each PLL used in
different SoCs.
Signed-off-by: Manikandan Muralidharan <[email protected]>
Signed-off-by: Varshini Rajendran <[email protected]>
|
|
The use of the unsigned variable 'i' as a loop index leads to the test
for i being non-negative always being true. Instead declare 'i' as an
int so that the for loop will terminate as expected.
If the original for loop completes 'i' will be 1 past the end of the
array so decrement it in the subsequent error path to prevent an out of
bounds access occurring.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
|
|
The variable 'index' is declared as unsigned but used to receive the
return value of a function returning 'int'. This value is then tested
for being less than zero to detect an error condition but as index is
unsigned this can never be true. Change the variable 'index' to be an
int so that the error condition can be detected.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
|
|
Add clock support for SAMA7D65
Signed-off-by: Ryan Wanner <[email protected]>
[[email protected]: add Fractional PLL core
output range]
Signed-off-by: Romain Sioen <[email protected]>
[[email protected]: adapt driver to upstream]
Signed-off-by: Varshini Rajendran <[email protected]>
|
|
Update the MAX PLL and master CLK ID to support sama7d65
SoC family.
Signed-off-by: Ryan Wanner <[email protected]>
|
|
Add PMC driver support for sam9x7 SoC family
Signed-off-by: Varshini Rajendran <[email protected]>
[[email protected]: Add peripheral clock id for pmecc]
Signed-off-by: Balamanikandan Gunasundar <[email protected]>
|
|
The clk_register function logs an error if parent_name is missing from the
Device Tree.On the SAM9X7, the main_rc node is omitted to stay aligned with
the Linux Device Tree.Remove the parent_name check in at91_clk_main_rc()
to allow it to pass NULL when the parent is not specified.
Signed-off-by: Manikandan Muralidharan <[email protected]>
|
|
Add support for hardware dividers for PLL IDs.In sam9x7 SoC,
PLL_ID_PLLA and PLL_ID_PLLA_DIV2 has /2 hardware dividers
each.
fcorepllack -----> HW Div = 2 -+--> fpllack
|
+--> HW Div = 2 ---> fplladiv2ck
Signed-off-by: Varshini Rajendran <[email protected]>
|
|
Add support for different core clock frequency input ranges
for different PLL IDs in the PLL driver and align sam9x60, sama7g5 SOC
platforms.
Signed-off-by: Varshini Rajendran <[email protected]>
|
|
As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.
Reported-by: Jonas Karlman <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
|
|
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.
This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.
Reported-by: Jonas Karlman <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
|
|
Remove <common.h> from this driver directory and when needed
add missing include files directly.
Signed-off-by: Tom Rini <[email protected]>
|
|
This function is a no-op. Remove it.
Signed-off-by: Sean Anderson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
|
|
Now that we have time conversion defines from in time.h there is no need
for each driver to define their own version.
Signed-off-by: Igor Prusov <[email protected]>
Reviewed-by: Svyatoslav Ryhel <[email protected]> # tegra
Reviewed-by: Eugen Hristev <[email protected]> #at91
Reviewed-by: Caleb Connolly <[email protected]> #qcom geni
Reviewed-by: Stefan Bosch <[email protected]> #nanopi2
Reviewed-by: Patrice Chotard <[email protected]>
|
|
Arrays are not cleared entirely because ARRAY_SIZE
returns the number of elements in an array, not the size
in bytes.
This commit fixes the calls to memset by providing the
array size in bytes instead of the number of elements
in the array.
Signed-off-by: Francois Berder <[email protected]>
|
|
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
devfdt_get_addr_ptr instead of the devfdt_get_addr function in
the various files in the drivers directory that cast to a pointer.
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
In order for some of the functionalities, such as the USB clocks,
to work properly we need some clocks to be properly initialised
at the very beginning of booting.
Signed-off-by: Sergiu Moga <[email protected]>
Reviewed-by: Claudiu Beznea <[email protected]>
Signed-off-by: Claudiu Beznea <[email protected]>
|
|
Clock setup was intended for setting clocks at boot time on SAMA7G5,
e.g. for root clocks like PLLs, that were used to feed IPs needed alive
in u-boot (e.g. Ethernet clock feed by a PLL). Export this functionality
to all at91 clocks as it may be necessary on other SoCs.
Signed-off-by: Claudiu Beznea <[email protected]>
|
|
Register into DM the clocks required to properly enable USB functionality
within the bootloader.
Signed-off-by: Sergiu Moga <[email protected]>
Reviewed-by: Claudiu Beznea <[email protected]>
Signed-off-by: Claudiu Beznea <[email protected]>
|
|
Implement sam9x60 USB clock driver. This clock has
three parents: PLLA, UPLL and MAINXTAL. The driver is
aware of the three possible parents with the help of the
two mux tables provied to the driver during the registration
of the clock.
Signed-off-by: Sergiu Moga <[email protected]>
Reviewed-by: Claudiu Beznea <[email protected]>
Signed-off-by: Claudiu Beznea <[email protected]>
|
|
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do
not easily transition to Kconfig. In many cases they likely should come
from the device tree instead. Move these out of CONFIG namespace and in
to CFG namespace.
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
ddrck and qspick should have mck_div as parent clocks to be in sync with
linux driver.
Signed-off-by: Mihai Sain <[email protected]>
Reviewed-by: Claudiu Beznea <[email protected]>
|
|
This converts most CCF drivers to use generic ops. imx6q is the only
outlier, where we retain the existing functionality by moving the check to
request().
Signed-off-by: Sean Anderson <[email protected]>
Reviewed-by: Claudiu Beznea <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[ fixed missing include for at91 ]
Signed-off-by: Sean Anderson <[email protected]>
|
|
Signed-off-by: Wolfgang Denk <[email protected]>
|
|
Split master clock in 2 controlling block: one for prescaler one for
divider. This will allow referencing correctly the CPU clock and
master clock in device trees.
Reported-by: Eugen Hristev <[email protected]>
Fixes: a64862284f65 ("clk: at91: sam9x60: add support compatible with
CCF")
Signed-off-by: Claudiu Beznea <[email protected]>
|
|
- Merge the patch to take <asm/global_data.h> out of <common.h>
|
|
Revert changes in at91 compat.c that cause u-boot to fail booting on
sama5d4_xplained and sama5d2_xplained
Log below:
<debug_uart>
No serial driver found
Could not initialize timer (err -19)
Could not initialize timer (err -19)
Could not initialize timer (err -19)
Could not initialize timer (err -19)
Could not initialize timer (err -19)
Could not initialize timer (err -19)
Could not initialize timer (err -19)
Could not initialize timer (err -19)
Fixes: a2703ce10c ("dm: Remove uses of device_bind_offset()")
Cc: Simon Glass <[email protected]>
Signed-off-by: Eugen Hristev <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
Move this out of the common header and include it only where needed. In
a number of cases this requires adding "struct udevice;" to avoid adding
another large header or in other cases replacing / adding missing header
files that had been pulled in, very indirectly. Finally, we have a few
cases where we did not need to include <asm/global_data.h> at all, so
remove that include.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
|
|
Prepare v2021.01-rc5
Signed-off-by: Tom Rini <[email protected]>
|
|
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <[email protected]>
|
|
This name is far too long. Rename it to remove the 'data' bits. This makes
it consistent with the platdata->plat rename.
Signed-off-by: Simon Glass <[email protected]>
|
|
Rename this to be consistent with the change from 'platdata'.
Signed-off-by: Simon Glass <[email protected]>
|
|
We use 'priv' for private data but often use 'platdata' for platform data.
We can't really use 'pdata' since that is ambiguous (it could mean private
or platform data).
Rename some of the latter variables to end with 'plat' for consistency.
Signed-off-by: Simon Glass <[email protected]>
|
|
This construct is quite long-winded. In earlier days it made some sense
since auto-allocation was a strange concept. But with driver model now
used pretty universally, we can shorten this to 'auto'. This reduces
verbosity and makes it easier to read.
Coincidentally it also ensures that every declaration is on one line,
thus making dtoc's job easier.
Signed-off-by: Simon Glass <[email protected]>
|
|
This function is not needed since the standard device_bind() can be used
instead.
Signed-off-by: Simon Glass <[email protected]>
|
|
Remove the parsing of atmel,main-osc-bypass DT property as the SAM9X60
have no support for crystal oscillator bypass. Setting this bit might
affect the device functionality.
Fixes: a64862284f65 ("clk: at91: sam9x60: add support compatible with CCF")
Signed-off-by: Claudiu Beznea <[email protected]>
|
|
This SoC has the 5th divisor for the mck0 master clock.
Adapt the characteristics accordingly.
Reported-by: Mihai Sain <[email protected]>
Signed-off-by: Eugen Hristev <[email protected]>
Reviewed-by: Claudiu Beznea <[email protected]>
|
|
clk-master can have 5 divisors with a field width of 3 bits
on some products.
Change the mask and number of divisors accordingly.
Reported-by: Mihai Sain <[email protected]>
Signed-off-by: Eugen Hristev <[email protected]>
Reviewed-by: Claudiu Beznea <[email protected]>
|
|
Add SAM9X60 clock support compatible with CCF.
Signed-off-by: Claudiu Beznea <[email protected]>
|
|
Necessary for dev_xxx.
Signed-off-by: Tom Rini <[email protected]>
|
|
Add clock support for SAMA7G5.
Signed-off-by: Claudiu Beznea <[email protected]>
|
|
Add generic clock ops to be used by every AT91 PMC driver
built on top of CCF.
Signed-off-by: Claudiu Beznea <[email protected]>
|
|
Add clk-generic driver compatible with common clock framework.
Signed-off-by: Claudiu Beznea <[email protected]>
|
|
Add clk-peripheral compatible with common clock framework.
Signed-off-by: Claudiu Beznea <[email protected]>
|
|
Add clk-system driver compatible with common clock framework.
Signed-off-by: Claudiu Beznea <[email protected]>
|
|
Add clk-programmable driver compatible with common clock framework.
Signed-off-by: Claudiu Beznea <[email protected]>
|
|
Add UTMI support for SAMA7G5. SAMA7G5's UTMI control is done via
XTALF register. Values written at bits 2..0 in this register
correspond to the on board crystal oscillator frequency.
Signed-off-by: Claudiu Beznea <[email protected]>
|
