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Add some VLP clocks needed by the PMIC on MT8189 and similar SoCs.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260323-mtk-mt8391-initial-support-v3-1-19dd92f4543f@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Change the pericfg priv_auto size to mtk_clk_priv. The driver is
registered using mtk_common_clk_infrasys_init() which expect that
struct.
The old value of struct mtk_cg_priv was larger, so there was no issue
out of bounds access.
Also replace tab with space to be consistent with the surrounding code.
Reported-by: Julien Stephan <[email protected]>
Closes: https://lore.kernel.org/u-boot/CAEHHSvYMiCZ4jAXp6jEhg6AhZ5Dv3_Ak-8H1mT7S2FPD3_X7dw@mail.gmail.com/
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260313-clk-mtk-fix-priv-auto-size-v1-1-bc649e1b301a@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Remove the CLK_PARENT_XTAL flag and related code. These have no more
users.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Replace all uses of CLK_XTAL with CLK_PAD_CLK26M.
This avoids declaring the same parent clock two different ways and will
eventually let us remove CLK_PARENT_XTAL completely.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Replace all uses of CLK_XTAL with CLK_PAD_CLK26M.
This avoids declaring the same parent clock two different ways and will
eventually let us remove CLK_PARENT_XTAL completely.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Replace all uses of CLK_XTAL with CLK_PAD_CLK26M.
This avoids declaring the same parent clock two different ways and will
eventually let us remove CLK_PARENT_XTAL completely.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Replace all uses of CLK_XTAL with CLK_PAD_CLK26M.
This avoids declaring the same parent clock two different ways and will
eventually let us remove CLK_PARENT_XTAL completely.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Replace all uses of CLK_XTAL with CLK_PAD_CLK26M.
This avoids declaring the same parent clock two different ways and will
eventually let us remove CLK_PARENT_XTAL completely.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Replace all uses of CLK_XTAL with CLK_PAD_CLK26M.
This avoids declaring the same parent clock two different ways and will
eventually let us remove CLK_PARENT_XTAL completely.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Replace all uses of CLK_XTAL with CLK_PAD_CLK26M.
This avoids declaring the same parent clock two different ways and will
eventually let us remove CLK_PARENT_XTAL completely.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Replace all uses of CLK_XTAL with CLK_PAD_CLK40M.
This will eventually let us remove CLK_PARENT_XTAL completely.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Replace all uses of CLK_XTAL with CLK_PAD_CLK40M.
This will eventually let us remove CLK_PARENT_XTAL completely.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Replace all uses of CLK_XTAL with CLK_PAD_CLK40M.
This will eventually let us remove CLK_PARENT_XTAL completely.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Replace all uses of CLK_XTAL with CLK_PAD_CLK40M.
This will eventually let us remove CLK_PARENT_XTAL completely.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Replace all uses of CLK_XTAL with CLK_PAD_CLK40M.
This will eventually let us remove CLK_PARENT_XTAL completely.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Replace all uses of CLK_XTAL with CLK_PAD_CLK26M.
This avoids declaring the same parent clock two different ways and will
eventually let us remove CLK_PARENT_XTAL completely.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Replace all uses of CLK_XTAL with CLK_PAD_CLK25M.
This avoids declaring the same parent clock two different ways and will
eventually let us remove CLK_PARENT_XTAL completely.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Replace the hard-coded xtal rate for PLL parents with struct mtk_parent.
This avoids declaring the same clock rate in multiple places and will
allow future drivers to use an arbitrary clock.
The variable is renamed to something that better indicate what the field
is actually used for.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Convert the mt8195 clock driver to use ext_clock_rates.
Now that we have the ext_clock_rates feature and also mux clock parents
have been converted to struct mtk_parent, we can remove the hack of
adding "missing" topckgen clocks. Instead we can use the proper parents.
The topckgen ID map is still needed though because the upstream
dt-bindings didn't use the conventional number ordering by clock type
for these.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260309-clk-mtk-mt8188-drop-extra-top-clocks-v1-2-6ee4743a8465@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Convert the mt8188 clock driver to use ext_clock_rates.
Now that we have the ext_clock_rates feature and also mux clock parents
have been converted to struct mtk_parent, we can remove the hack of
adding "missing" topckgen clocks. Instead we can use the proper parents.
The topckgen ID map is still needed though because the upstream
dt-bindings didn't use the conventional number ordering by clock type
for these.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260309-clk-mtk-mt8188-drop-extra-top-clocks-v1-1-6ee4743a8465@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Drop the clock ID map for MT8365 TOPCKGEN clocks.
Previously, we didn't have the EXT clock feature, so we needed the map.
Now we can replace it with the new feature to avoid the map.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Refactor two identical functions for getting mux clock rates. The
functions are renamed and moved to the section of the code that contains
other common functions.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-16-a4760f5b0a80@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Remove CLK_PARENT_MIXED and all dead code paths related to it.
All mux clocks have been converted to use struct mtk_parent (the
parent_flags field of the parent/parent_flags union). Use of this
struct was indicated by CLK_PARENT_MIXED. Now, this is always the case
and we can drop the flag and the union. All MUX_MIXED* macros are
change to use the equivalent MUX* macros since we no longer need to
set the flag.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-15-a4760f5b0a80@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Remove the CLK_BYPASS_XTAL flag completely.
It was a bit of a hack that was meant to handle mux clocks that had
mixed parents (e.g. XTAL and TOPCKGEN). The idea was that if you didn't
have CLK_XTAL as a parent, then you were supposed to add the
CLK_BYPASS_XTAL flag to the clock tree. There are likely a number of
drivers missing this since it is not intuitive.
In the meantime, we have introduced the CLK_PARENT_MIXED flag which
handles this more robustly. All of the affected drivers (the ones
without CLK_BYPASS_XTAL) have been updated to use CLK_PARENT_MIXED, so
the CLK_BYPASS_XTAL flag is no longer needed on other drivers.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-14-a4760f5b0a80@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Convert all parent clock arrays to use struct mtk_parent. This will
allow us to simplify core code later by having only one possible data
type for mux parent arrays.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-13-a4760f5b0a80@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Convert all parent clock arrays to use struct mtk_parent. This will
allow us to simplify core code later by having only one possible data
type for mux parent arrays.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-12-a4760f5b0a80@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Convert all parent clock arrays to use struct mtk_parent. This will
allow us to simplify core code later by having only one possible data
type for mux parent arrays.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-11-a4760f5b0a80@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Convert all parent clock arrays to use struct mtk_parent. This will
allow us to simplify core code later by having only one possible data
type for mux parent arrays.
Reviewed-by: Macpaul Lin <[email protected]>
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-10-a4760f5b0a80@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Convert all parent clock arrays to use struct mtk_parent. This will
allow us to simplify core code later by having only one possible data
type for mux parent arrays.
Reviewed-by: Macpaul Lin <[email protected]>
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-9-a4760f5b0a80@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Convert all parent clock arrays to use struct mtk_parent. This will
allow us to simplify core code later by having only one possible data
type for mux parent arrays.
Reviewed-by: Macpaul Lin <[email protected]>
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-8-a4760f5b0a80@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Convert all parent clock arrays to use struct mtk_parent. This will
allow us to simplify core code later by having only one possible data
type for mux parent arrays.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-7-a4760f5b0a80@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Convert all parent clock arrays to use struct mtk_parent. This will
allow us to simplify core code later by having only one possible data
type for mux parent arrays.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-6-a4760f5b0a80@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Convert all parent clock arrays to use struct mtk_parent. This will
allow us to simplify core code later by having only one possible data
type for mux parent arrays.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-5-a4760f5b0a80@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Convert all parent clock arrays to use struct mtk_parent. This will
allow us to simplify core code later by having only one possible data
type for mux parent arrays.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-4-a4760f5b0a80@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Convert all parent clock arrays to use struct mtk_parent. This will
allow us to simplify core code later by having only one possible data
type for mux parent arrays.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-3-a4760f5b0a80@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Convert all parent clock arrays to use struct mtk_parent. This will
allow us to simplify core code later by having only one possible data
type for mux parent arrays.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-2-a4760f5b0a80@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Convert all parent clock arrays to use struct mtk_parent. This will
allow us to simplify core code later by having only one possible data
type for mux parent arrays.
Reviewed-by: Macpaul Lin <[email protected]>
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-1-a4760f5b0a80@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Explicitly set the CLK_PARENT_XTAL flag for fixed factor clocks.
Prior to this, it was assumed that clock ID 0 was CLK_XTAL and other
IDs used a different clock tree when no parent was explicitly set.
Making the parent explicit will allow us to remove this confusing
behavior in the future.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260306-clk-mtk-remove-clk-bypass-xtal-flag-v2-8-b253b49f17b2@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Move repeated *_PARENT() macros from chip-specific .c files to the
common mtk-clk.h file.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260306-clk-mtk-remove-clk-bypass-xtal-flag-v2-4-b253b49f17b2@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Add new MUX_GATE_MIXED and MUX_GATE_MIXED_FLAGS macros for mixed parent
muxes that have a gate. These will be used in a few drivers where we
already have this type of mux clocks.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260306-clk-mtk-remove-clk-bypass-xtal-flag-v2-3-b253b49f17b2@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Rename CLK_DOMAIN_SCPSYS to CLK_MUX_DOMAIN_SCPSYS to make it more clear
that this flag only applies to MUX clocks and not other clock types.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260306-clk-mtk-remove-clk-bypass-xtal-flag-v2-2-b253b49f17b2@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Rename HAVE_RST_BAR to CLK_PLL_HAVE_RST_BAR. This makes it more clear
that this flag only applies to PLL clocks. Also add a blank line between
CLK_PLL_HAVE_RST_BAR and the CLK_MUX_ macros to keep the grouping of the
flags consistent.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260306-clk-mtk-remove-clk-bypass-xtal-flag-v2-1-b253b49f17b2@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Add new clock driver for MedaiTek MT8189 and compatible SoCs.
Signed-off-by: Chris Chen <[email protected]>
Co-developed-by: David Lechner <[email protected]>
Reviewed-by: Julien Stephan <[email protected]>
Reviewed-by: Macpaul Lin <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Add a new MUX_MIXED_CLR_SET_UPD_FLAGS() macro. This is the same as
MUX_CLR_SET_UPD_FLAGS() except that it uses the parent_flags member
of the union instead of parent.
This will be needed by the incoming mt8189 clock driver.
Reviewed-by: Julien Stephan <[email protected]>
Reviewed-by: Macpaul Lin <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Add support for external clock parent type in MediaTek clock driver to
allow multiple external clock sources.
This is intended to eventually replace CLK_PARENT_XTAL which only allows
a single external clock source. Replacing CLK_PARENT_XTAL is not trivial
since it would required touching all chip-specific drivers. So that is
saved for another day.
Before this change, the only way to add additional external clocks was
to use a clock ID mapping and add the external clock in the fixed clocks
portion of the CLK_PARENT_TOPCKGEN clocks. After this change, such hacks
are no longer necessary and external clocks can be added in a cleaner
way.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Add helper functions to check if a clock ID corresponds to a particular
clock type (mux, gate, fdiv). This simplifies the code and makes it more
readable.
Additionally, it removes the restriction that fdivs_offs < muxes_offs <
gates_offs by making the checking more strict in some places. This will
allow future drivers to not have to define a mapping to meet this
requirement.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Refactor duplicate parent rate lookup code into a common function.
Instead of relying on rules like X is always the parent of Y, we use
the driver ops pointer to make sure we are actually getting the correct
parent clock device. This allows the same function to be called from
different clock types and will allow future chip-specific clock drivers
to not have to follow the rules as strictly.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Fix the private data type struct type in a couple of infrasys clock
functions.
struct mtk_cg_priv is a superset of struct mtk_clk_priv and has the same
layout at the beginning so there was no compile errors or runtime bugs.
This could only be found by inspecting the code.
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Change CLK_TOP_CLK13M rate from 130_000_000 to 13_000_000 and
CLK_TOP_CLK26M rate from 260_000_000 to 26_000_000. As the names
suggest, these clocks are 13/26 MHz, not 130/260 MHz.
Fixes: 5e9bbbdab003 ("clk: mediatek: mt8188: add missing fixed clock")
Fixes: 11f3cc46322a ("clk: mediatek: add MT8188 clock driver")
Reviewed-by: Julien Stephan <[email protected]>
Tested-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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