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GATE_CLK() in its current state is unsafe: A simple write to the clock
enable register does not guarantee that the clock is immediately running.
Without polling the clock status, we may issue writes to registers before
the necessary clocks start running. This doesn't seem to cause issues in
U-Boot at the moment, but for example removing the CLK_OFF polling in TF-A
for the SMMU clocks on DB410c reliably triggers an exception during boot.
Make it possible to poll the branch clock status register, by adding a new
GATE_CLK_POLLED() macro that takes the extra register address. Existing
usages work just as before, without polling the clock status. Ideally all
usages should be updated to specify the correct poll address in the future.
The Qualcomm naming for these clocks is "branch" and not "gate", but let's
keep the existing naming for now to avoid confusion until all others
drivers have been converted.
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: Stephan Gerhold <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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The other clock enable functions in clock-qcom.c use setbits_le32() to
read/modify/write the enable registers. Use the same for qcom_gate_clk_en()
to simplify the code a bit.
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: Stephan Gerhold <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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This avoids having to inline it separately into every single clock driver,
when U-Boot is built with support for multiple SoCs.
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: Stephan Gerhold <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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The PCIe PIPE clock requires a special setup function to
mux & enable the clock from the PCIe PHY before the PHY
has enabled the clock.
Import the clk_phy_mux_enable() from the Linux driver to
use the same implementation regarding the PIPE clock.
Signed-off-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Caleb Connolly <[email protected]>
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Add support for dumping a few of the clocks used on Qualcomm platforms.
Naming the Global PLL's, Root Clock Generators, and gate clocks.
This helps a lot with platform bringup and feature enablement by making
it easy to sanity check that the clocks are programmed correctly.
== Usage ==
Enable CONFIG_CMD_CLK and "#define LOG_DEBUG" at the top of
qcom-<soc>.c.
The "clk dump" command should print the states of all the gates, GPLLs
and RCGs for your SoC.
== Glossary ==
RCG: Root Clock Generator
* Takes in some fairly arbitrary high freq clock (configurable clock
source and options for taking just even pulses and other things)
* Output frequency = input_freq * (m/n) * (1/d) where m/n are arbitrary
8 or 16-bit values (depending on the RCG), and d is a number (with
support for .5 offsets).
GPLL: Global Phase Locked Loop
* Crystal as input
* integer multiplier + exponent part (2^-40)
Gate: Simple on/off clock
* Put between RCGs and the peripherals they power
* Required to allow for correct power sequencing
If you do the maths manually using the equations from "clk dump", the
numbers should roughly line up by they're likely to be out by a handful
of MHz. They output is formatted so that it can be pasted directly into
the python interpreter.
Signed-off-by: Caleb Connolly <[email protected]>
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Drop all duplicate newlines. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.
Reported-by: Jonas Karlman <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.
This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.
Reported-by: Jonas Karlman <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Remove <common.h> from this driver directory and when needed
add missing include files directly.
Signed-off-by: Tom Rini <[email protected]>
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The RCG registers always have the same offsets, so only store the base
CMD register address and calculate the others relative to that.
Reviewed-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Some devices like the UART and clock controller reference an RPM(h)
power domain. We don't support this device in U-Boot, so add
DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the
power domain.
Reviewed-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Now sub-drivers for particular SoCs can register them as power domain
drivers. This is needed for upcoming SM8150 support, because it needs
to power up the Ethernet module.
Signed-off-by: Volodymyr Babchuk <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Reviewed-by: Caleb Connolly <[email protected]>
[caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN]
Signed-off-by: Caleb Connolly <[email protected]>
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The current behaviour does a bitwise OR of the previous and new
divider values, this is wrong as some bits may be set already. We
need to clear all the divider bits before applying new ones.
This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards.
Signed-off-by: Volodymyr Babchuk <[email protected]>
Reviewed-by: Caleb Connolly <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
[caleb: minor wording fix]
Signed-off-by: Caleb Connolly <[email protected]>
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The RCG divider field takes a value of (2*h - 1) where h is the divisor.
This allows fractional dividers to be supported by calculating them at
compile time using a macro.
However, the clk_rcg_set_rate_mnd() function was also performing the
calculation. Clean this all up and consistently use the F() macro to
calculate these at compile time and properly support fractional divisors.
Additionally, improve clk_bcr_update() to timeout with a warning rather
than hanging the board, and make the freq_tbl struct and helpers common
so that they can be reused by future platforms.
Reviewed-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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This property is needed on some platforms to ensure that only the
relevant bits are set in the M/N/D registers.
Reviewed-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Currently, it isn't possible to build clock drivers for more than one
platform due to how the msm_enable() and msm_set_rate() callbacks are
implemented.
Extend qcom_clk_data to include function pointers for these and convert
all platforms to use them.
Previously, clock drivers relied on include/configs/<board.h> to include the
board specific sysmap header, however as most of the header contents are clock
driver related, import the contents directly into each clock driver and
remove the header. The only exception here is the dragonboard820c board file
which includes some pinctrl macros, those are also inlined.
Reviewed-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
[caleb: remove additional sysmap-sdm845.h mention]
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Qualcomm's clock controller blocks actually do much more than it
says on the tin.. They provide clocks, resets and power domains.
Currently, U-Boot requires one to spawn 2 separate devices for
controlling clocks and resets, both spanning the same register space.
Refactor the code to make it work with just a single DT node, making
it compatible with upstream Linux bindings and dropping the dedicated
reset driver in favour of including it in the clock driver.
Heavily inspired by Renesas code for a similar hw block.
[caleb: moved drivers to clk/qcom, added reset driver and adjusted bind
logic. Imported qcom,gcc-ipq4019.h from Linux]
Signed-off-by: Konrad Dybcio <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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This driver is just a stub, but it's necessary to support the upcoming
reset driver changes.
Reviewed-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Clock drivers don't belong here, move them to the right place and
declutter mach-snapdragon a bit.
To de-couple these drivers from specific "target" platforms, add
additional config options to enable each clock driver gated behind a
common CLK_QCOM option and enable them by default for the respective
targets. This will make future work easier as we move towards a generic
Qualcomm target.
Reviewed-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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