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Add clock driver for RK3506.
Imported from vendor U-Boot linux-6.1-stan-rkr6 tag with minor
adjustments and fixes for mainline.
Signed-off-by: Finley Xiao <[email protected]>
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add clock driver support for Rockchip RK3576 SoC.
Signed-off-by: Elaine Zhang <[email protected]>
[adapted to mainline u-boot]
Signed-off-by: Heiko Stuebner <[email protected]>
Reviewed-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add clock driver for RK3528.
Imported from vendor U-Boot linux-6.1-stan-rkr5 tag with minor
adjustments and fixes for mainline.
Signed-off-by: Joseph Chen <[email protected]>
Signed-off-by: Finley Xiao <[email protected]>
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add clock driver support for Rockchip RK3588 SoC.
Signed-off-by: Elaine Zhang <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
Signed-off-by: Kever Yang <[email protected]>
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Add clock driver support for Rockchip RV1126 SoC.
Signed-off-by: Joseph Chen <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add the clock driver for the rk3066 platform.
Derived from the rk3288 and rk3188 driver it
supports only a bare minimum to bring up the system
to reduce the TPL size for:
SDRAM clock configuration.
The boot devices NAND, EMMC, SDMMC, SPI.
A UART for the debug messages (fixed) at 115200n8.
A SARADC for the recovery button.
A TIMER for the delays (fixed).
There's support for two possible frequencies,
the safe 600MHz which will work with default pmic settings and
will be set to get away from the 24MHz default and
the maximum of 1.416Ghz, which boards can set if they
were able to get pmic support for it.
After the clock tree is set during the TPL probe
there's no parent update support.
In OF_REAL mode the drivers ns16550.c and dw-apb-timer.c
obtain the (fixed) clk_get_rate from the clock driver
instead of platdata.
The rk3066 cru node has a number of assigned-clocks properties
that call the .set_rate() function. Add them to the list so that
they return a 0 instead of -ENOENT.
Signed-off-by: Paweł Jarosz <[email protected]>
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Sean Anderson <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add rk3568 clock driver and cru structure definition.
Signed-off-by: Elaine Zhang <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add clk controller driver for RK3308 SOC.
This patch depends on Elaine's pll patch[0].
[0]http://patchwork.ozlabs.org/patch/1183718/
Signed-off-by: Andy Yan <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Common PLL setup function, compatible with different SOC.
Mainly for the subsequent new SOC use.
Signed-off-by: Elaine Zhang <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The px30 contains 2 separate clock controllers, pmucru and cru.
Add drivers for them.
Signed-off-by: Kever Yang <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Complete in the drivers directory the work started with
commit 83d290c56fab ("SPDX: Convert all of our single
license tags to Linux Kernel style").
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Patrick Delaunay <[email protected]>
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Add rk3128 clock driver and cru structure definition.
Signed-off-by: Kever Yang <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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Add clock driver init support for:
- cpu, bus clock init;
- emmc, sdmmc clock;
- ddr clock;
Signed-off-by: Kever Yang <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
Fixed format specified (%x -> %p) in clk_rk322x.c:
Signed-off-by: Philipp Tomsich <[email protected]>
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Add clock driver support for Rockchip rv1108 soc
Signed-off-by: Andy Yan <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add driver to setup the various PLLs and peripheral
clocks on the RK3368.
Signed-off-by: Andy Yan <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add rk3328 clock driver and cru structure definition.
Signed-off-by: William Zhang <[email protected]>
Signed-off-by: Kever Yang <[email protected]>
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Add a driver for setting up and modifying the various PLLs and peripheral
clocks on the RK3188.
Signed-off-by: Heiko Stuebner <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Kever Yang <[email protected]>
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With the number of Rockchip clock drivers increasing, don't clutter up
the core drivers/clk directory with them and instead move them out of
the way into a separate subdirectory.
Suggested-by: Simon Glass <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>
Acked-by: Simon Glass <[email protected]>
Updated for rk3399:
Signed-off-by: Simon Glass <[email protected]>
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