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The devm alloc functions that we have may follow the Linux kernel model
where allocations are (almost always) automatically free()'d. However,
quite often we don't enable, in full U-Boot, the tracking and free()'ing
functionality. This in turn leads to memory leaks because the driver
author expects that since the functions have the same name as in the
Linux Kernel they have the same behavior. In turn we then get
functionally correct commits such as commit 00e1fed93c8c ("firmware:
ti_sci: Fix memory leaks in devm_ti_sci_get_of_resource") that manually
add these calls. Rather than manually tracking allocations and
implementing free()s, rework things so that we follow expectations by
enabling the DEVRES functionality (outside of xPL phases).
This turns DEVRES from a prompted symbol to a symbol that must be
select'd, and we now remove our non-managed alloc/free functions from
outside of xPL builds.
Reviewed-by: Michael Trimarchi <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Add support for FudanMicro FM25S01A SPI NAND.
This driver is ported from linux v6.18 and tested on a MT7981 board.
Link: https://lore.kernel.org/linux-mtd/[email protected]/
Reviewed-by: Mikhail Kshevetskiy <[email protected]>
Signed-off-by: Tianling Shen <[email protected]>
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Continuous reading may result in multiple flash pages reading in one
operation. Unfortunately, not all spinand controllers support such
large reading. They will read less data. Unfortunately, the operation
can't be continued.
In this case:
* disable continuous reading on this (not good enough) spi controller
* repeat reading in regular mode.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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reading fails
Continuous reading may result in multiple flash pages reading in one
operation. Typically only one flash page has read/written (a little bit
more than 2-4 Kb), but continuous reading requires the spi controller
to read up to 512 Kb in one operation without toggling CS in beetween.
Roughly speaking spi controllers can be divided on 2 categories:
* spi controllers without dirmap acceleration support
* spi controllers with dirmap acceleration support
Firt of them will have issues with continuous reading if restriction on
the transfer length is implemented in the adjust_op_size() handler.
Second group often supports acceleration of single page only reading.
Thus enabling of continuous reading can break flash reading.
This patch tries to create dirmap for continuous reading first and
fallback to regular reading if spi controller refuses to create it.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Continuous mode is only supported for data reads, thus writing
requires only single flash page mapping.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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This makes the U-Boot SPI NAND driver almost the same as in Linux
6.17-rc1. The only major differences are:
* support of ECC engines. The Linux driver supports different ECC
engines while U-Boot uses on-die ECC only.
* per operation maximum SPI bus frequency
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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There is already a manufacturer hook, which is manufacturer specific but
not chip specific. We no longer have access to the actual NAND identity
at this stage so let's add a per-chip configuration hook to align the
chip configuration (if any) with the core's setting.
This is a port of linux commit
da55809ebb45 ("mtd: spinand: Add a ->configure_chip() hook")
Signed-off-by: Miquel Raynal <[email protected]>
Signed-off-by: Mikhail Kshevetskiy <[email protected]> # U-Boot port
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Since commit 3d1f08b032dc ("mtd: spinand: Use the external ECC engine
logic") the spinand_write_page() function ignores the errors returned
by spinand_wait(). Change the code to propagate those up to the stack
as it was done before the offending change.
This is a port of linux commit
091d9e35b85b ("mtd: spinand: propagate spinand_wait() errors from spinand_write_page()")
Signed-off-by: Gabor Juhos <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
Signed-off-by: Mikhail Kshevetskiy <[email protected]> # U-Boot port
Signed-off-by: Michael Trimarchi <[email protected]>
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Currently the best variant picked in the first one in the list provided
in the manufacturer driver. This worked well while all operations where
performed at the same speed, but with the introduction of DTR transfers
this no longer works correctly.
Let's continue iterating over all the alternatives, even if we find a
match, keeping a reference over the theoretically fastest
operation. Only at the end we can tell which variant is the best.
This logic happening only once at boot.
The patch is based on linux commit
666c299be696 (mtd: spinand: Enhance the logic when picking a variant)
created by Miquel Raynal <[email protected]>
The code was a bit restricted in the functionality since not all
required functionality is supported in the u-boot.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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The code was ported from linux-6.15
based on a linux commit c06b1f753bea (mtd: spinand: add OTP support)
created by Martin Kurbanov <[email protected]>
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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When the host ECC fails to correct the data error of NAND device,
there's a special read for data recovery method which can be setup
by the host for the next read. There are several retry levels that
can be attempted until the lost data is recovered or definitely
assumed lost.
This is the port of linux commit
f2cb43c98010 (mtd: spinand: Add read retry support)
Signed-off-by: Cheng Ming Lin <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
Signed-off-by: Mikhail Kshevetskiy <[email protected]> # U-Boot port
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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The code was ported from linux-6.12. The original continuous reading
support was implemented by Miquel Raynal <[email protected]>
in linux commit 631cfdd0520d (mtd: spi-nand: Add continuous read support).
Here is an original patch description:
--------------------------------------
A regular page read consist in:
- Asking one page of content from the NAND array to be loaded in the
chip's SRAM,
- Waiting for the operation to be done,
- Retrieving the data (I/O phase) from the chip's SRAM.
When reading several sequential pages, the above operation is repeated
over and over. There is however a way to optimize these accesses, by
enabling continuous reads. The feature requires the NAND chip to have a
second internal SRAM area plus a bit of additional internal logic to
trigger another internal transfer between the NAND array and the second
SRAM area while the I/O phase is ongoing. Once the first I/O phase is
done, the host can continue reading more data, continuously, as the chip
will automatically switch to the second SRAM content (which has already
been loaded) and in turns trigger the next load into the first SRAM area
again.
From an instruction perspective, the command op-codes are different, but
the same cycles are required. The only difference is that after a
continuous read (which is stopped by a CS deassert), the host must
observe a delay of tRST. However, because there is no guarantee in Linux
regarding the actual state of the CS pin after a transfer (in order to
speed-up the next transfer if targeting the same device), it was
necessary to manually end the continuous read with a configuration
register write operation.
Continuous reads have two main drawbacks:
* They only work on full pages (column address ignored)
* Only the main data area is pulled, out-of-band bytes are not
accessible. Said otherwise, the feature can only be useful with on-die
ECC engines.
Performance wise, measures have been performed on a Zynq platform using
Macronix SPI-NAND controller with a Macronix chip (based on the
flash_speed tool modified for testing sequential reads):
- 1-1-1 mode: performances improved from +3% (2-pages) up to +10% after
a dozen pages.
- 1-1-4 mode: performances improved from +15% (2-pages) up to +40% after
a dozen pages.
This series is based on a previous work from Macronix engineer Jaime
Liao.
--------------------------------------
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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SkyHigh spinand device has ECC enable bit in configuration register but
it must be always enabled. If ECC is disabled, read and write ops
results in undetermined state. For such devices, a way to avoid raw
access is needed.
Introduce SPINAND_NO_RAW_ACCESS flag to advertise the device does not
support raw access. In such devices, the on-die ECC engine ops returns
error to I/O request in raw mode.
Checking and marking BBM need to be cared as special case, by adding
fallback mechanism that tries read/write OOB with ECC enabled.
This is a port of linux commit
6d9d6ab3a82a (mtd: spinand: Introduce a way to avoid raw access)
Signed-off-by: Takahiro Kuwano <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
Signed-off-by: Mikhail Kshevetskiy <[email protected]> # U-Boot port
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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We don't have to call spinand_write_enable_op() in spinand_markbad() as
it is called in spinand_write_page().
This is the port of linux commit
c6858779f1f5 (mtd: spinand: Remove write_enable_op() in markbad())
Signed-off-by: Takahiro Kuwano <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
Signed-off-by: Mikhail Kshevetskiy <[email protected]> # U-Boot port
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Add two flags for inserting the Plane Select bit into the column
address during the write_to_cache and the read_from_cache operation.
Add the SPINAND_HAS_PROG_PLANE_SELECT_BIT flag for serial NAND flash
that require inserting the Plane Select bit into the column address
during the write_to_cache operation.
Add the SPINAND_HAS_READ_PLANE_SELECT_BIT flag for serial NAND flash
that require inserting the Plane Select bit into the column address
during the read_from_cache operation.
This is a port of linux commit
ca229bdbef29 (mtd: spinand: Add support for setting plane select bits)
Signed-off-by: Cheng Ming Lin <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
Link: https://lore.kernel.org/linux-mtd/[email protected]
Signed-off-by: Mikhail Kshevetskiy <[email protected]> # U-Boot port
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Reporting an unclean read from SPI-NAND only when the maximum number
of correctable bitflip errors has been hit seems a bit late.
UBI LEB scrubbing, which depends on the lower MTD device reporting
correctable bitflips, then only kicks in when it's almost too late.
Set bitflip_threshold to 75% of the ECC strength, which is also the
default for raw NAND.
This is a port of linux commit
1824520e7477 (mtd: spinand: set bitflip_threshold to 75% of ECC strength)
Signed-off-by: Daniel Golle <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
Link: https://lore.kernel.org/linux-mtd/2117e387260b0a96f95b8e1652ff79e0e2d71d53.1723427450.git.daniel@makrotopia.org
Signed-off-by: Mikhail Kshevetskiy <[email protected]> # U-Boot port
Signed-off-by: Michael Trimarchi <[email protected]>
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This makes the U-Boot SPI NAND driver almost the same as in Linux 6.10.
The only major difference is support of ECC engines. The Linux driver
supports different ECC engines while U-Boot uses on-die ECC only.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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changes:
* Move spinand_check_ecc_status(), spinand_noecc_ooblayout_ecc(),
spinand_noecc_ooblayout_free() and spinand_noecc_ooblayout close
to each other.
* some code formatting
* remove comments not present in linux driver
This aligns the code with Linux 6.10.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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No functional changes, just some refactoring to better match linux
kernel driver.
changes:
* move spinand configuration reading out from spinand_init_cfg_cache()
to separate function spinand_read_cfg()
* move spinand flash initialization to separate function
spinand_init_flash()
* move direct mapping initialization to the end of spinand_init()
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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This aligns the logic to match the Linux kernel implementation.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Use spinand_to_nand() and spinand_to_mtd() helpers instead of
nanddev_to_mtd() and direct access to spinand structure fields.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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This aligns spinand_wait() with the linux kernel. Instead of calling into
spi_mem_poll_status() which is not implemented in U-Boot, we code the
polling logic and make sure that schedule() is called periodically.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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The module misses MODULE_DEVICE_TABLE() for both SPI and OF ID tables
and thus never autoloads on ID matches.
Add the missing declarations.
Present since day-0 of spinand framework introduction.
This is a port of linux commit
25fefc88c71f ("mtd: spinand: core: add missing MODULE_DEVICE_TABLE()")
Signed-off-by: Alexander Lobakin <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
Link: https://lore.kernel.org/linux-mtd/[email protected]
Signed-off-by: Mikhail Kshevetskiy <[email protected]> # U-Boot port
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Use an enum to differentiate the type of I/O (reading or writing a
page). Also update the request iterator.
This is a port of linux commit
701981cab016 ("mtd: nand: Add a NAND page I/O request type")
Signed-off-by: Miquel Raynal <[email protected]>
Reviewed-by: Boris Brezillon <[email protected]>
Link: https://lore.kernel.org/linux-mtd/[email protected]
Signed-off-by: Mikhail Kshevetskiy <[email protected]> # U-Boot port
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Make use of the spi-mem direct mapping API to let advanced controllers
optimize read/write operations when they support direct mapping.
Based on a linux commit 981d1aa0697c ("mtd: spinand: Use the spi-mem dirmap API")
created by Boris Brezillon <[email protected]> with additional
fixes taken from Linux 6.10.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Adding support for:
GD5F1GQ4RExxG
GD5F2GQ4UExxG
GD5F2GQ4RExxG
GD5F1GQ5RExxG
GD5F2GQ5UExxG
GD5F2GQ5RExxG
GD5F4GQ6UExxG
GD5F4GQ6RExxG
GD5F1GM7UExxG
GD5F1GM7RExxG
GD5F2GM7UExxG
GD5F2GM7RExxG
GD5F4GM8UExxG
GD5F4GM8RExxG
GD5F2GQ5xExxH
GD5F1GQ5RExxH
GD5F1GQ4RExxH
Signed-off-by: Chuanhong Guo <[email protected]>
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Add Winbond W25N04KV flash support that use a different value to detect
ECC bitflip.
Signed-off-by: Christian Marangi <[email protected]>
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Call SPI setup_for_spinand() if supported and defined to configure the
SPI slave for the attached NAND. This is needed to configure the SPI
with the NAND page size and spare size for correct configuration of the
device.
Call it as soon as the NAND is detected to correctly handle SPI
controller with select_op_variant detection.
Signed-off-by: Christian Marangi <[email protected]>
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UBI block is virtual block device, which is an abstraction
over MTD layer. Therefore it is logical to use it in combination
with MTD drivers.
Signed-off-by: Alexey Romanov <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Bind SPI-NAND driver to MTD block driver.
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Alexey Romanov <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Drop all duplicate newlines. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.
Reported-by: Jonas Karlman <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.
This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.
Reported-by: Jonas Karlman <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Remove <common.h> from this driver directory and when needed
add missing include files directly.
Reviewed-by: William Zhang <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Add support for XTX XT26G0xA and XT26xxxD. The driver is ported from
linux-6.7.1. This driver is tested on Banana BPI-R3 with XT26G01A and
XT26G12D.
Link: https://lore.kernel.org/all/[email protected]
Signed-off-by: Bruce Suen <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Dario Binacchi <[email protected]>
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Adaptation of Linux commit d74c36480a67
This patch adds support for ESMT F50L1G41LB and F50D1G41LB.
It seems that ESMT likes to use random JEDEC ID from other vendors.
Their 1G chips uses 0xc8 from GigaDevice and 2G/4G chips uses 0x2c from
Micron. For this reason, the ESMT entry is named esmt_c8 with explicit
JEDEC ID in variable name.
Datasheets:
https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/F50L1G41LB(2M).pdf
https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/F50D1G41LB(2M).pdf
Signed-off-by: Igor Prusov <[email protected]>
Signed-off-by: Chuanhong Guo <[email protected]>
Signed-off-by: Martin Kurbanov <[email protected]>
Signed-off-by: Dmitry Rokosov <[email protected]>
Tested-by: Martin Kurbanov <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Add support of Winbond W25N02KV flash
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
Link: https://lore.kernel.org/linux-mtd/[email protected]
Signed-off-by: Frieder Schrempf <[email protected]> (U-Boot port)
Link: https://lore.kernel.org/all/[email protected]
Signed-off-by: Dario Binacchi <[email protected]>
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Winbond uses 3 bytes to identify flash: vendor_id, dev_id_0, dev_id_1,
but current driver uses only first 2 bytes of it for devices
identification. As result Winbond W25N02KV flash (id_bytes: EF, AA, 22)
is identified as W25N01GV (id_bytes: EF, AA, 21).
Fix this by adding missed identification bytes.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
Link: https://lore.kernel.org/linux-mtd/[email protected]
Signed-off-by: Frieder Schrempf <[email protected]> (U-Boot port)
Link: https://lore.kernel.org/all/[email protected]
Signed-off-by: Dario Binacchi <[email protected]>
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This adds more supported spinand devices from the Linux kernel
implementation.
This does not include the latest kernel implementation as this would
require a substantial amount of extra work due to the missing
ECC engine abstraction layer in U-Boot.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Signed-off-by: Frieder Schrempf <[email protected]> (commit message)
Link: https://lore.kernel.org/all/[email protected]
Signed-off-by: Dario Binacchi <[email protected]>
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This brings us closer to the current Linux kernel implementation of
the spinand core and makes backporting features and fixes easier.
This does not include the latest kernel implementation as this would
require a substantial amount of extra work due to the missing
ECC engine abstraction layer in U-Boot.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Signed-off-by: Frieder Schrempf <[email protected]> (add commit message)
Link: https://lore.kernel.org/all/[email protected]
Signed-off-by: Dario Binacchi <[email protected]>
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Currently there are 3 different variants of read_id implementation:
1. opcode only. Found in GD5FxGQ4xF.
2. opcode + 1 addr byte. Found in GD5GxGQ4xA/E
3. opcode + 1 dummy byte. Found in other currently supported chips.
Original implementation was for variant 1 and let detect function
of chips with variant 2 and 3 to ignore the first byte. This isn't
robust:
1. For chips of variant 2, if SPI master doesn't keep MOSI low
during read, chip will get a random id offset, and the entire id
buffer will shift by that offset, causing detect failure.
2. For chips of variant 1, if it happens to get a devid that equals
to manufacture id of variant 2 or 3 chips, it'll get incorrectly
detected.
This patch reworks detect procedure to address problems above. New
logic do detection for all variants separatedly, in 1-2-3 order.
Since all current detect methods do exactly the same id matching
procedure, unify them into core.c and remove detect method from
manufacture_ops.
This is a rework of Chuanhong Guo <[email protected]> patch
submitted to linux kernel
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Signed-off-by: Frieder Schrempf <[email protected]>
Link: https://lore.kernel.org/all/[email protected]
Signed-off-by: Dario Binacchi <[email protected]>
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This old patch was marked as deferred. Bring it back to life, to continue
towards the removal of common.h
Move this out of the common header and include it only where needed.
Signed-off-by: Simon Glass <[email protected]>
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In case ID is not found in manufacturer table, the raw ID is
printed using %*phN format which is not supported by lib/vsprintf.c.
The information displayed doesn't reflect the raw ID return by the
unknown spi-nand.
Use %02x format instead, as done in spi-nor-core.c.
For example, before this patch:
ERROR: spi-nand: spi_nand flash@0: unknown raw ID f74ec040
after
ERROR: spi-nand: spi_nand flash@0: unknown raw ID 00 c2 26 03
Fixes: 0a6d6bae0386 ("mtd: nand: Add core infrastructure to support SPI NANDs")
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Acked-by: Michael Trimarchi <[email protected]>
Signed-off-by: Dario Binacchi <[email protected]>
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Globally replace all occurances of WATCHDOG_RESET() with schedule(),
which handles the HW_WATCHDOG functionality and the cyclic
infrastructure.
Signed-off-by: Stefan Roese <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Tom Rini <[email protected]> [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm]
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According to datasheet, the upper four bits are reserved or used for
reflecting the ECC status of the accumulated pages. The error bits
number for the worst segment of the current page is encoded on lower
four bits. Fix it by masking the upper bits.
This same issue has been already fixed in the linux kernel by:
"mtd: spinand: macronix: Fix ECC Status Read"
(sha1: f4cb4d7b46f6409382fd981eec9556e1f3c1dc5d)
Apply the same fix in the U-Boot driver.
Signed-off-by: Haolin Li <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Macronix NAND Flash devices are available in different configurations
and densities.
MX"35" means SPI NAND
MX35"UF" , UF meands 1.8V
MX35LF"2G" , 2G means 2Gbits
MX35LF2G"E4" , E4 means internal ECC and Quad I/O(x4)
MX35UF4GE4AD/MX35UF2GE4AD/MX35UF1GE4AD are 1.8V 4G/2Gbit serial
NAND flash device with 8-bit on-die ECC
https://www.mxic.com.tw/Lists/Datasheet/Attachments/7983/MX35UF4GE4AD,%201.8V,%204Gb,%20v0.00.pdf
MX35UF2GE4AC/MX35UF1GE4AC are 1.8V 2G/1Gbit serial
NAND flash device with 8-bit on-die ECC
https://www.mxic.com.tw/Lists/Datasheet/Attachments/7974/MX35UF2GE4AC,%201.8V,%202Gb,%20v1.0.pdf
Validated via normal(default) and QUAD mode by read, erase, read back,
on Xilinx Zynq PicoZed FPGA board which included Macronix
SPI Host(drivers/spi/spi-mxic.c).
Signed-off-by: Jaime Liao <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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In case of big area read/write on spi nand, watchdog timeout may occurs.
To fix that, add WATCHDOG_RESET() in spinand_mtd_read() and
spinand_mtd_write() to ensure that watchdog is reset.
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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The relevant changes to the already existing GD5F1GQ4UExxG support has
been determined by consulting the GigaDevice product change notice
AN-0392-10, version 1.0 from November 30, 2020.
As the overlaps are huge, variable names have been generalized
accordingly.
Apart form the lowered ECC strength (4 instead of 8 bits per 512 bytes),
the new device ID, and the extra quad IO dummy byte, no changes had to
be taken into account.
New hardware features are not supported, namely:
- Power on reset
- Unique ID
- Double transfer rate (DTR)
- Parameter page
- Random data quad IO
The inverted semantic of the "driver strength" register bits, defaulting
to 100% instead of 50% for the Q5 devices, got ignored as the driver has
never touched them anyway.
The no longer supported "read from cache during block erase"
functionality is not reflected as the current SPI NAND core does not
support it anyway.
Implementation has been tested on MediaTek MT7688 based GARDENA smart
Gateways using both, GigaDevice GD5F1GQ5UEYIG and GD5F1GQ4UBYIG.
Signed-off-by: Reto Schneider <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Acked-by: Jagan Teki <[email protected]>
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The datasheet only lists one dummy byte in the 0xEB operation for the
following chips:
* GD5F1GQ4xExxG
* GD5F1GQ4xFxxG
* GD5F1GQ4UAYIG
* GD5F4GQ4UAYIG
Reto Schneider:
- Linux patch ported to U-Boot
- Checked for compatibility with GD5F1GQ4xBxxG
- Fixed operation code in original commit message (0xEH -> 0xEB)
Signed-off-by: Reto Schneider <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Acked-by: Jagan Teki <[email protected]>
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Driver model: make some udevice fields private
Driver model: Rename U_BOOT_DEVICE et al.
dtoc: Tidy up and add more tests
ns16550 code clean-up
x86 and sandbox minor fixes for of-platdata
dtoc prepration for adding build-time instantiation
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