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Add support for reading DRAM size information from PMUGRF os_reg2 reg.
Signed-off-by: Jonas Karlman <[email protected]>
Tested-by: Aaron Griffith <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add ddr driver for rk3576 to get the ram capacity.
Signed-off-by: Heiko Stuebner <[email protected]>
Reviewed-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add support for reading DRAM size information from PMUGRF os_reg18 reg.
Compared to most Rockchip SoCs the RK3528 use os_reg18 for DRAM info,
instead of os_reg2.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add ddr driver for rk3588 to get the ram capacity.
Co-developed-by: Jonas Karlman <[email protected]>
Signed-off-by: Jonas Karlman <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add DDR driver for Rockchip RV1126 SoC.
Signed-off-by: YouMin Chen <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add rockchip rk3066 sdram driver
Signed-off-by: Paweł Jarosz <[email protected]>
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add the driver for rk3568 u-boot to get sdram capacity.
Signed-off-by: Joseph Chen <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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A dm based dram driver for rk3308 u-boot
to get capacity.
Signed-off-by: Andy Yan <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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For there are some structures and functions are common for all rockchip SoCs,
migrate to use the common code so that we can clean up reduandent codes.
Signed-off-by: YouMin Chen <[email protected]>
Signed-off-by: Kever Yang <[email protected]>
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RK3328 has a similar controller and phy with PX30, so we can use the
common driver for it and remove the duplicate codes.
Signed-off-by: YouMin Chen <[email protected]>
Signed-off-by: Kever Yang <[email protected]>
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Add the sdram driver for PX30 to support ddr3, ddr4, lpddr2 and lpddr3.
For TPL_BUILD, the driver implement full dram init and without DM
support due to the limit of internal SRAM size.
For SPL and U-Boot proper, it's a simple driver with dm for get
dram_info like other SoCs.
Signed-off-by: YouMin Chen <[email protected]>
Signed-off-by: Kever Yang <[email protected]>
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The functions for dram info print are part of common code.
Signed-off-by: YouMin Chen <[email protected]>
Signed-off-by: Kever Yang <[email protected]>
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There are some function like os_reg setting, capacity detect functions,
can be used as common code for different Rockchip SoCs, add a
sdram_common.c for all these functions.
Signed-off-by: YouMin Chen <[email protected]>
Signed-off-by: Kever Yang <[email protected]>
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Add sdram driver to handle debug across rockchip SoCs.
This would help to improve code debugging feature for
sdram drivers in rockchip family, whoever wants to
debug the driver should call these core debug code on
their respective platform sdram drivers.
Signed-off-by: Jagan Teki <[email protected]>
Signed-off-by: YouMin Chen <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Right now sdram drivers in rockchip SoC are built based
on the SoC configs which may not be an adequate solutions
while adding common or debug driver.
So, add meaningful Kconfig options start with rk3399.
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Complete in the drivers directory the work started with
commit 83d290c56fab ("SPDX: Convert all of our single
license tags to Linux Kernel style").
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Patrick Delaunay <[email protected]>
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RK3128 support up to 2GB DDR3 sdram, one channel, 32bit data width.
This patch is only used for U-Boot, but not for SPL which will
comes later, maybe after we merge all the common code into a common
file.
Signed-off-by: Kever Yang <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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Add driver for rk322x to support sdram initialize in SPL.
Signed-off-by: Kever Yang <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.
Signed-off-by: Kever Yang <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.
Signed-off-by: Kever Yang <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.
Signed-off-by: Kever Yang <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.
Signed-off-by: Kever Yang <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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This adds a DRAM controller driver for the RK3368 and places it in
drivers/ram/rockchip (where the other DM-enabled DRAM controller
drivers for rockchip devices should also be moved eventually).
At this stage, only the following feature-set is supported:
- DDR3
- 32-bit configuration (i.e. fully populated)
- dual-rank (i.e. no auto-detection of ranks)
- DDR3-1600K speed-bin
This driver expects to run from a TPL stage that will later return to
the RK3368 BROM. It communicates with later stages through the
os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR
init code).
Unlike other DMC drivers for RK32xx and RK33xx parts, the required
timings are calculated within the driver based on a target frequency
and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this
time).
The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0)
register for controlling the operation of its (single-channel) DRAM
controller in the GRF block. This provides for selecting DDR3, mobile
DDR modes, and control low-power operation.
As part of this change, DDRC0_CON0 is also added to the GRF structure
definition (at offset 0x600).
Signed-off-by: Philipp Tomsich <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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