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In mci_send_cmd the pointer 'data' is optional so guard its use with a
NULL check to prevent any attempt to dereference it when not provided.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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Remove duplicate checks on status from mci_data_read and mci_data_write
which are guaranteed to be true as exiting the above do..while loop
above requires that to be so.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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If the test in the for loop is never matched then the variable 'match'
will never be assigned to. Provide an initial value so this cannot be a
problem.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
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The use of the unsigned variable 'i' as a loop index leads to the test
for i being non-negative always being true. Instead declare 'i' as an
int so that the for loop will terminate as expected.
If the original for loop completes 'i' will be 1 past the end of the
array so decrement it in the subsequent error path to prevent an out of
bounds access occurring.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
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The variable 'index' is declared as unsigned but used to receive the
return value of a function returning 'int'. This value is then tested
for being less than zero to detect an error condition but as index is
unsigned this can never be true. Change the variable 'index' to be an
int so that the error condition can be detected.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
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In atmel_qspi_transfer(), the status register is polled with:
imr = QSPI_SR_INSTRE | QSPI_SR_CSR;
return readl_poll_timeout(aq->regs + QSPI_SR, sr,
(sr & imr) == imr,
ATMEL_QSPI_TIMEOUT);
However, this is racy: QSPI_SR_INSTRE can be set before QSPI_SR_CSR,
and will then be cleared by the read. If that happens, the condition
"(sr & imr) == imr" can never be true, and the function times out.
This race condition is avoided in at91bootstrap by accumulating the
status bits across reads until both bits have been observed:
/* Poll INSTruction End and Chip Select Rise flags. */
imr = (QSPI_SR_INSTRE | QSPI_SR_CSR);
sr = 0;
do {
udelay(1);
sr |= qspi_readl(qspi, QSPI_SR) & imr;
} while ((--timeout) && (sr != imr));
Update U-Boot's atmel_qspi_transfer() to use the same pattern,
ensuring that both flags are observed even if they are not set
simultaneously.
Signed-off-by: Ramin Moussavi <[email protected]>
[[email protected]: remove 'sr' and fix commit msg]
Signed-off-by: Eugen Hristev <[email protected]>
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The name of the pin function was changed last minute in the DT, from
emac0 to gmac0.
Adjust the name we use in the pinctrl driver accordingly.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
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The Linux pinctrl-sx150 was originally written as a GPIO driver
and fully rewritten by me as a Pinctrl driver and extended by
other contributors.
Fixup the Copyright header style and correctly report the
Copyright headers from the Linux driver.
Signed-off-by: Neil Armstrong <[email protected]>
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Fixes: 5451504256d3 ("pinctrl: gpio: sx150x: add Semtech SX150x I2C GPIO expander and pinctrl driver")
Signed-off-by: Chali Anis <[email protected]>
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In gpio_dwapb_bind plat is used to reference memory allocated by
devm_kcalloc but it is attempted to be freed using kfree. Instead free
this memory using the correct devm_kfree function.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Acked-by: Quentin Schulz <[email protected]>
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The function dev_read_u32_default does not return an error and the
variable 'val' is unsigned so testing for >= 0 will always be true. It
looks like the code was attempting to return -1 if xtal-load-pf was not
present but that cannot work. Instead use dev_read_u32 which returns an
error code separately from writing the value into the passed pointer.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Fixes: 260777fc2333 ("clk: cdce9xx: add support for cdce9xx clock synthesizer")
Acked-by: Quentin Schulz <[email protected]>
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This adds more common functions found on other architectures that will
allow for more compile-testing of drivers. These are either dummy
functions as we do not need them or mappings to existing functions,
similar to how other architectures handle it.
Signed-off-by: Tom Rini <[email protected]>
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This driver requires Apple rtkit headers in order to build. Express
that requirement in Kconfig as well.
Signed-off-by: Tom Rini <[email protected]>
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A large number of PCI controllers cannot build without access to some
platform specific header files. Express those requirements in Kconfig as
well.
Signed-off-by: Tom Rini <[email protected]>
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This driver references the SZ_ macros while relying on an indirection
inclusion of <linux/sizes.h>. Add the missing include directly.
Signed-off-by: Tom Rini <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-socfpga
This pull request introduces initial U-Boot support for Agilex7 M-series, along
with several enhancements and cleanups across existing Agilex platforms. Key
changes include new board support, DDR driver additions, updated device trees,
and broader SoCFPGA SPL improvements.
Highlights:
- Agilex7 M-series bring-up:
- Basic DT support and board initialization for Agilex7 M-series SoC and
SoCDK.
- New sdram_agilex7m DDR driver with UIBSSM mailbox support and HBM support.
- Clock driver support for Agilex7 M-series.
- New defconfig: socfpga_agilex7m_defconfig.
- Agilex and Agilex5 enhancements:
- Improved SPL support: ASYNC interrupt enabling, system manager init
refactor, and cold scratch register usage.
- Updated firewall probing and watchdog support in SPL.
- Cleaned up DDR code, added secure region support for ATF, and improved warm
reset handling.
- Device Tree and config updates:
- Migration to upstream Linux DT layout for Agilex platforms.
- Consolidated socfpga_agilex_defconfig and removed deprecated configs.
- Platform-specific environment variables for Distro Boot added.
- Driver fixes and cleanups:
- dwc_eth_xgmac and clk-agilex cleanup and improvements.
- Several coverity and style fixes.
Contributions in this PR are from Alif Zakuan Yuslaimi, Tingting Meng, and
Andrew Goodbody. This patch set has been tested on Agilex 5 devkit, Agilex
devkit and Agilex7m devkit.
Passing all pipeline tests at SoCFPGA U-boot custodian
https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/27318
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27314
- Several Smatch reported fixes.
- Enable the temperature command on imx8ulp-evk.
- Fix mx8mm_fracpll_tbl.
- Make optee packaging optional for imx8m.
- Reuse and export low_drive_freq_update() on imx9.
- Enable USB OTG ID pin pull up in SPL on dh-imx6.
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Fix wrong memory size calculation in clamshell mode
Signed-off-by: Tingting Meng <[email protected]>
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Clean up bit-shift by zero bit
Signed-off-by: Tingting Meng <[email protected]>
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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This is for new platform enablement for Agilex7 M-series.
Add DDR driver for Agilex7 M-series. This driver is designed to support
DDR and HBM memory. The official HBM handoff is not ready yet, therefore
hardcoded handoff is used for HBM driver validation on mUDV board.
Signed-off-by: Tingting Meng <[email protected]>
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Add uibssm mailbox driver for Agilex7 M-series. HPS will interact with UIB
and HBM subsystem through software defined mailbox interface.
HPS can retrieve HBM memory interface calibration status, UIB
configuration, memory interfae configuration, trigger calibration and etc
with the list of supported mailbox command type and opcode.
Signed-off-by: Tingting Meng <[email protected]>
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Agilex7 M-series reuse the clock driver from Agilex.
Signed-off-by: Tingting Meng <[email protected]>
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Put all slave CPUs (CPU1-3) into WFI mode. Master CPU (CPU0) writes
the magic word into system manager's scratch register to indicate
the system has performed L2 reset and request reset manager to
perform hardware handshake and then trigger L2 reset. CPU0 put
itself into WFI mode. L2 reset will reboot all HPS CPU cores after
which all HPS cores are in WFI mode. L2 reset is followed by warm
reset request by SPL via RMR_EL3 system register.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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The DDR data rate must be set correctly in the DDRIOCTRL
register according to the Actual Clock Frequency (ACF) value.
By enabling the reading of ACF value from bit 18 of the boot
scratch register during initialization, the DDR data rate is
able to be configured accurately.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Remove redundant code for MPFE CSR firewall disabled as this was
already set in DTreg dts.
Signed-off-by: Tien Fong Chee <[email protected]>
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Setting up firewall regions based on SDRAM memory banks configuration
(up to CONFIG_NR_DRAM_BANKS banks) instead of using whole address space.
First 1 MiB (0 to 0xfffff) of SDRAM is configured as secure region,
other address spaces are non-secure regions. The ARM Trusted Firmware (ATF)
image is located in this first 1 MiB memory region. So, this can prevent
software executing at non-secure state EL0-EL2 and non-secure masters
access to secure region.
Add common function for firewall setup and reuse for all SoC64 devices.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Replace cm_wait_for_fsm() function with wait_for_bit_le32() function
which supports accurate timeout.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Enable watchdog as early as possible after clock initialization
which is set at 10 seconds.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Update the ARMv8 generic timer frequency register (cntfrq_el0)
with the actual hardware timer frequency (COUNTER_FREQUENCY_REAL).
The generic timer frequency was set to 0x200000000 during boot clk
which needs to be set to 0x400000000 when transition from boot clk
to PLL clk.
This will ensure that subsequent timer operations are based on the
correct frequency, ensuring accurate timekeeping.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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In dwxgmac_of_get_mac_mode there is a test for mac_mode which will
return if false. After this point mac_mode is guaranteed to be true so
there is no need to test for this. Remove that test.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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In xgmac_probe there is a direct return after the point where unwind
gotos start to be used to undo actions performed by earlier code. Use
the appropriate unwind goto instead.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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If the allocation if the bounce buffer fails, virtio_free_pages is called
with a random value from the stack.
Ensure that vring.size is initialized.
Fixes: 37e53db38bdb ("virtio: Allocate bounce buffers for devices with VIRTIO_F_IOMMU_PLATFORM")
Addresses-Coverity-ID: 453314 Uninitialized scalar variable
Signed-off-by: Heinrich Schuchardt <[email protected]>
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s25_s28_mdp_ready() returns 1 when spansion_sr_ready() returns negative
value (error code). Fix this problem by following Linux implementation.
Fixes: 1c3dd193b5b ("mtd: spi-nor-core: Add fixups for Cypress s25hl-t/s25hs-t")
Reported-by: Hiroyuki Saito <[email protected]>
Signed-off-by: Takahiro Kuwano <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
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The 'blks' variable in scsi_read/write/erase functions is updated
regardless of pass/fail of the scsi operation . If the scsi operation
fails, 'blkcnt' is updated using an incorrect value of 'blks'. This
wrong 'blkcnt' is returned to the caller and it assumes all blocks were
processed correctly.
Fix this by updating the 'blks' variable only if the scsi operation
succeeds.
Signed-off-by: Balaji Selvanathan <[email protected]>
Signed-off-by: Varadarajan Narayanan <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
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In fecmxc_probe if a timeout is detected when resetting the chip no
error code is set before taking the error exit. This could lead to a
silent failure. Instead set an error code.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
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In sc_seco_secvio_dgo_config there is a check for data being NULL but
this occurs after data has already been dereferenced. All callers of the
function provide a valid pointer for data so no need for the NULL check.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
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Add setting default temperatures to the weak version of
get_cpu_temp_grade so these values will not be used uninitialised.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
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For an unknown pll type the error path neglects to free the memory just
allocated. Add the free.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
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Various fixes for smatch warnings, the i2c one might be also coming in
via Heiko / I2C tree, let me know if there is conflict.
There is also W77Q51NW SPI NOR ID support, with the DT portion omitted
for now.
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In rswitch_probe the error detection after the call to devm_clk_get is
very wrong. It checks the value of ret which is uninitialised at that
point. Instead it should be using the macros for including errors into
pointers.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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Add IDs for Winbond W77Q51NW, 512M-bit Secure Serial Flash Memory
with Post-Quantum Cryptography, Dual/Quad SPI, QPI and DTR . The
flash part is similar to W25Q512NWM .
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
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In rcar_iic_xfer if nmsgs == 0 the ret will not be assigned to. As ret
will always be 0 if the for loop is entered, may as well just return 0.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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In rcar_clk_set_rate64_div_table the unsigned variable 'value' is used
to receive the return value from rcar_clk_get_table_val which returns an
int and then attempts to test for being less than 0, which can never be
true. Instead declare value as an int so the code can behave as
expected. Also remove initial values from 'value' and 'div' as they are
not needed.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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Add i3c command file to support select, get i3c device
target list, read and write operation.
Signed-off-by: Dinesh Maniyam <[email protected]>
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Fix the I3C device with spike filter unable to detect issue by setting
tHIGH_INIT to 200ns for first broadcast address.
This is according to MIPI SPEC 1.1.1 for first broadcast address
which is already part of linux upstreamed patch.
Signed-off-by: Dinesh Maniyam <[email protected]>
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Picked linux i3c driver upstraming patch to fix the issue to
probe for i3c controller without slave device attached.
With this fix, the ret check will be on command error and will success
without slave device attached.
Signed-off-by: Dinesh Maniyam <[email protected]>
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Add s simple test for the I3C uclass in sandbox.
Signed-off-by: Dinesh Maniyam <[email protected]>
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Enable the Kconfig and Makefile for the MIPI DWI3C driver.
hs: fixed typo on drivers/i3c/master/Kconfig
Signed-off-by: Dinesh Maniyam <[email protected]>
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Add new i3c driver to U-Boot drivers.
Signed-off-by: Dinesh Maniyam <[email protected]>
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Enable i3c general uclass driver. This uclass driver will have
genaral read and write api to call the specific i3c driver.
Signed-off-by: Dinesh Maniyam <[email protected]>
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