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Age	Commit message (Collapse)	Author
2015-05-07	ARM: socfpga: move SoC headers to mach-socfpga/include/mach	Masahiro Yamada
	Move headers to mach-socfpga as well. Signed-off-by: Masahiro Yamada <[email protected]>
2014-12-06	arm: socfpga: Add missing DW master SPI clock prototyp to clock_manager.h	Stefan Roese
	Signed-off-by: Stefan Roese <[email protected]> Cc: Chin Liang See <[email protected]> Cc: Dinh Nguyen <[email protected]> Cc: Vince Bridgers <[email protected]> Cc: Marek Vasut <[email protected]> Acked-by: Pavel Machek <[email protected]>
2014-10-06	arm: socfpga: clock: Sync with reference code	Marek Vasut
	Add the missing pieces from the reference clock code from Altera. This puts the code on par with the Altera U-Boot fork for all but the SDRAM self-refresh bits, which are not part of this patch. Signed-off-by: Marek Vasut <[email protected]> Cc: Chin Liang See <[email protected]> Cc: Dinh Nguyen <[email protected]> Cc: Albert Aribaud <[email protected]> Cc: Tom Rini <[email protected]> Cc: Wolfgang Denk <[email protected]> Cc: Pavel Machek <[email protected]> Acked-by: Pavel Machek <[email protected]>
2014-10-06	arm: socfpga: clock: Clean up bit definitions	Marek Vasut
	Clean up the clock code definitions so they are aligned with mainline standards. There are no functional changes in this patch. Signed-off-by: Marek Vasut <[email protected]> Cc: Chin Liang See <[email protected]> Cc: Dinh Nguyen <[email protected]> Cc: Albert Aribaud <[email protected]> Cc: Tom Rini <[email protected]> Cc: Wolfgang Denk <[email protected]> Cc: Pavel Machek <[email protected]> Acked-by: Pavel Machek <[email protected]>
2014-10-06	arm: socfpga: clock: Add code to read clock configuration	Pavel Machek
	Add the entire bulk of code to read out clock configuration from the SoCFPGA CPU registers. This is important for MMC, QSPI and UART drivers as otherwise they cannot determine the frequency of their upstream clock. Signed-off-by: Pavel Machek <[email protected]> Signed-off-by: Marek Vasut <[email protected]> Cc: Chin Liang See <[email protected]> Cc: Dinh Nguyen <[email protected]> Cc: Albert Aribaud <[email protected]> Cc: Tom Rini <[email protected]> Cc: Wolfgang Denk <[email protected]> Cc: Pavel Machek <[email protected]> V2: Fixed the L4 MP clock divider and synced the clock code with latest rocketboards codebase (thanks Dinh for pointing this out)
2014-10-06	arm: socfpga: clock: Implant order into bit definitions	Marek Vasut
	The bit definitions for clock manager are complete chaos. Implement some basic logical order into them. Signed-off-by: Marek Vasut <[email protected]> Cc: Chin Liang See <[email protected]> Cc: Dinh Nguyen <[email protected]> Cc: Albert Aribaud <[email protected]> Cc: Tom Rini <[email protected]> Cc: Wolfgang Denk <[email protected]> Cc: Pavel Machek <[email protected]> Acked-by: Pavel Machek <[email protected]>
2014-08-29	socfpga: fix clock manager register definition	Pavel Machek
	Structure defining clock manager hardware was wrong, leading to wrong registers being accessed and hang in MMC init. This fixes structure to match hardware. Signed-off-by: Pavel Machek <[email protected]>
2014-04-07	socfpga: Adding Clock Manager driver	Chin Liang See
	Clock Manager driver will be called to reconfigure all the clocks setting based on user input. The input are passed to Preloader through handoff files Signed-off-by: Chin Liang See <[email protected]> Cc: Albert Aribaud <[email protected]> Cc: Tom Rini <[email protected]> Cc: Wolfgang Denk <[email protected]> CC: Pavel Machek <[email protected]> Cc: Dinh Nguyen <[email protected]> Acked-by: Pavel Machek <[email protected]>