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Add clock support for SAMA7D65
Signed-off-by: Ryan Wanner <[email protected]>
[[email protected]: add Fractional PLL core
output range]
Signed-off-by: Romain Sioen <[email protected]>
[[email protected]: adapt driver to upstream]
Signed-off-by: Varshini Rajendran <[email protected]>
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Add PMC driver support for sam9x7 SoC family
Signed-off-by: Varshini Rajendran <[email protected]>
[[email protected]: Add peripheral clock id for pmecc]
Signed-off-by: Balamanikandan Gunasundar <[email protected]>
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Implement sam9x60 USB clock driver. This clock has
three parents: PLLA, UPLL and MAINXTAL. The driver is
aware of the three possible parents with the help of the
two mux tables provied to the driver during the registration
of the clock.
Signed-off-by: Sergiu Moga <[email protected]>
Reviewed-by: Claudiu Beznea <[email protected]>
Signed-off-by: Claudiu Beznea <[email protected]>
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Add SAM9X60 clock support compatible with CCF.
Signed-off-by: Claudiu Beznea <[email protected]>
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Add clock support for SAMA7G5.
Signed-off-by: Claudiu Beznea <[email protected]>
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Add clk-generic driver compatible with common clock framework.
Signed-off-by: Claudiu Beznea <[email protected]>
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Add clk-peripheral compatible with common clock framework.
Signed-off-by: Claudiu Beznea <[email protected]>
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Add clk-system driver compatible with common clock framework.
Signed-off-by: Claudiu Beznea <[email protected]>
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Add clk-programmable driver compatible with common clock framework.
Signed-off-by: Claudiu Beznea <[email protected]>
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Add clk-utmi driver compatible with common clock framework.
Signed-off-by: Claudiu Beznea <[email protected]>
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Add clk-master driver compatible with common clock framework.
Signed-off-by: Claudiu Beznea <[email protected]>
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Add sam9x60-pll driver compatible with common clock framework.
Signed-off-by: Claudiu Beznea <[email protected]>
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Add clk-main driver compatible with common clock framework.
Signed-off-by: Claudiu Beznea <[email protected]>
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Add sckc driver compatible with common clock framework. Driver
implements slow clock support for SAM9X60 compatible IPs (in this
list it is also present SAMA7G5's slow clock IP).
Signed-off-by: Claudiu Beznea <[email protected]>
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Move clock code to compat.c to allow switching to CCF
without mixing CCF code with non CCF code. This prepares the
field for next commits.
Signed-off-by: Claudiu Beznea <[email protected]>
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As said in the SAMA5D2 datasheet, the PLLA clock must be divided
by 2 by writing the PLLADIV2 bit in PMC_MCKR, if the ratio between
PCK and MCK is 3 (MDIV = 3). This is the purpose of the driver.
Signed-off-by: Wenyou Yang <[email protected]>
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Add USB clock driver to configure the input clock and the divider
in the PMC_USB register to generate a 48MHz and a 12MHz signal to
the USB Host OHCI.
Signed-off-by: Wenyou Yang <[email protected]>
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The patch is referred to at91 clock driver of Linux, to make
the clock node descriptions in DT aligned with the Linux's.
Signed-off-by: Wenyou Yang <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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