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2026-07-29clk: mediatek: mt8516: use driver data to store the clock treeJulien Stephan
Pass each controller's struct mtk_clk_tree through the driver data and use the generic probe function for all the MT8516 clock drivers, instead of a dedicated probe per controller. The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since they rely on dedicated ops and on the parent bind() callback, but they now get their tree from the compatible data. No functional change intended. Signed-off-by: Julien Stephan <[email protected]> Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-20-23e907516010@baylibre.com Signed-off-by: David Lechner <[email protected]>
2026-07-29clk: mediatek: mt8516: deduplicate clock gate driversJulien Stephan
Describe the topckgen clock gates directly in a struct mtk_clk_tree, reference the tree from the driver data and use the generic mtk_clk_topckgen_ops instead of the dedicated clock gate ops. This stops using mtk_common_clk_gate_init() and struct mtk_cg_priv, which are scheduled for removal. No functional change intended. Signed-off-by: Julien Stephan <[email protected]> Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-19-23e907516010@baylibre.com Signed-off-by: David Lechner <[email protected]>
2026-07-29clk: mediatek: mt8183: use driver data to store the clock treeJulien Stephan
Pass each controller's struct mtk_clk_tree through the driver data and use the generic probe function for all the MT8183 clock drivers, instead of a dedicated probe per controller. The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since they rely on dedicated ops and on the parent bind() callback, but they now get their tree from the compatible data. No functional change intended. Signed-off-by: Julien Stephan <[email protected]> Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-18-23e907516010@baylibre.com Signed-off-by: David Lechner <[email protected]>
2026-07-29clk: mediatek: mt8183: deduplicate clock gate driversJulien Stephan
Describe the infracfg gates directly in a struct mtk_clk_tree, reference the tree from the driver data and use the generic mtk_clk_topckgen_ops instead of the dedicated clock gate ops. This stops using mtk_common_clk_gate_init() and struct mtk_cg_priv, which are scheduled for removal. No functional change intended. Signed-off-by: Julien Stephan <[email protected]> Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-17-23e907516010@baylibre.com Signed-off-by: David Lechner <[email protected]>
2026-07-29clk: mediatek: mt7988: use driver data to store the clock treeJulien Stephan
Pass each controller's struct mtk_clk_tree through the driver data and use the generic probe function for the MT7988 clock drivers, instead of a dedicated probe per controller. The fixed-pll, topckgen and infracfg controllers keep their own U_BOOT_DRIVER since they rely on dedicated ops and on the parent bind() callback, but they now get their tree from the compatible data. The topckgen probe still performs its SoC specific register tweaks. No functional change intended. Signed-off-by: Julien Stephan <[email protected]> Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-16-23e907516010@baylibre.com Signed-off-by: David Lechner <[email protected]>
2026-07-29clk: mediatek: mt7988: deduplicate clock gate driversJulien Stephan
MT7988 declares a separate U_BOOT_DRIVER, probe() function and compatible table for each clock gate controller, despite all of them sharing the same implementation. Describe the gates directly in each controller's struct mtk_clk_tree, reference the trees from the driver data and use the generic mtk_clk_topckgen_ops. The two sgmiisys controllers, which share the same DM flags and (absent) bind() callback, are merged into a single U_BOOT_DRIVER; ethdma and ethwarp keep their own drivers since they bind reset controllers at different offsets. This also stops using mtk_common_clk_gate_init() and struct mtk_cg_priv, which are scheduled for removal. No functional change intended. Signed-off-by: Julien Stephan <[email protected]> Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-15-23e907516010@baylibre.com Signed-off-by: David Lechner <[email protected]>
2026-07-29clk: mediatek: mt7987: use driver data to store the clock treeJulien Stephan
Pass each controller's struct mtk_clk_tree through the driver data and use the generic probe function for the MT7987 clock drivers, instead of a dedicated probe per controller. The fixed-pll, topckgen and infracfg controllers keep their own U_BOOT_DRIVER since they rely on dedicated ops and on the parent bind() callback, but they now get their tree from the compatible data. The topckgen probe still performs its SoC specific register tweaks. No functional change intended. Signed-off-by: Julien Stephan <[email protected]> Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-14-23e907516010@baylibre.com Signed-off-by: David Lechner <[email protected]>
2026-07-29clk: mediatek: mt7987: deduplicate clock gate driversJulien Stephan
Describe the ethsys gates directly in a struct mtk_clk_tree, reference the tree from the driver data and use the generic mtk_clk_topckgen_ops instead of the dedicated clock gate ops. This stops using mtk_common_clk_gate_init() and struct mtk_cg_priv, which are scheduled for removal. No functional change intended. Signed-off-by: Julien Stephan <[email protected]> Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-13-23e907516010@baylibre.com Signed-off-by: David Lechner <[email protected]>
2026-07-29clk: mediatek: mt7986: use driver data to store the clock treeJulien Stephan
Pass each controller's struct mtk_clk_tree through the driver data and use the generic probe function for the MT7986 clock drivers, instead of a dedicated probe per controller. The fixed-pll, topckgen and infracfg controllers keep their own U_BOOT_DRIVER since they rely on dedicated ops and on the parent bind() callback, but they now get their tree from the compatible data. The topckgen probe still performs its SoC specific register tweaks. No functional change intended. Signed-off-by: Julien Stephan <[email protected]> Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-12-23e907516010@baylibre.com Signed-off-by: David Lechner <[email protected]>
2026-07-29clk: mediatek: mt7986: deduplicate clock gate driversJulien Stephan
Describe the ethsys gates directly in a struct mtk_clk_tree, reference the tree from the driver data and use the generic mtk_clk_topckgen_ops instead of the dedicated clock gate ops. This stops using mtk_common_clk_gate_init() and struct mtk_cg_priv, which are scheduled for removal. No functional change intended. Signed-off-by: Julien Stephan <[email protected]> Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-11-23e907516010@baylibre.com Signed-off-by: David Lechner <[email protected]>
2026-07-29clk: mediatek: mt7981: use driver data to store the clock treeJulien Stephan
Pass each controller's struct mtk_clk_tree through the driver data and use the generic probe function for the MT7981 clock drivers, instead of a dedicated probe per controller. The fixed-pll, topckgen and infracfg controllers keep their own U_BOOT_DRIVER since they rely on dedicated ops and on the parent bind() callback, but they now get their tree from the compatible data. The topckgen probe still performs its SoC specific register tweaks. No functional change intended. Signed-off-by: Julien Stephan <[email protected]> Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-10-23e907516010@baylibre.com Signed-off-by: David Lechner <[email protected]>
2026-07-29clk: mediatek: mt7981: deduplicate clock gate driversJulien Stephan
MT7981 declares a separate U_BOOT_DRIVER, probe() function and compatible table for each clock gate controller, despite all of them sharing the same implementation. Describe the gates directly in each controller's struct mtk_clk_tree, reference the trees from the driver data and use the generic mtk_clk_topckgen_ops. The two sgmiisys controllers, which share the same DM flags and (absent) bind() callback, are merged into a single U_BOOT_DRIVER; ethsys keeps its own driver as it binds a reset controller. This also stops using mtk_common_clk_gate_init() and struct mtk_cg_priv, which are scheduled for removal. No functional change intended. Signed-off-by: Julien Stephan <[email protected]> Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-9-23e907516010@baylibre.com Signed-off-by: David Lechner <[email protected]>
2026-07-29clk: mediatek: mt7629: use driver data to store the clock treeJulien Stephan
Pass each controller's struct mtk_clk_tree through the driver data and use the generic probe function for all the MT7629 clock drivers, instead of a dedicated probe per controller. The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since they rely on dedicated ops and on the parent bind() callback, but they now get their tree from the compatible data. The apmixedsys probe still performs its SoC specific register tweaks. No functional change intended. Signed-off-by: Julien Stephan <[email protected]> Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-8-23e907516010@baylibre.com Signed-off-by: David Lechner <[email protected]>
2026-07-29clk: mediatek: mt7629: deduplicate clock gate driversJulien Stephan
MT7629 declares a separate U_BOOT_DRIVER, probe() function and compatible table for each clock gate controller, despite all of them sharing the same implementation. Describe the gates directly in each controller's struct mtk_clk_tree, reference the trees from the driver data and use the generic mtk_clk_topckgen_ops. Controllers that share the same DM flags and bind() callback are then merged: infracfg and pericfg into one pre-relocation driver, sgmiisys and ssusbsys into another. ethsys keeps its own driver as it binds a reset controller. While at it, this fixes a latent off-by-one in the infracfg gate lookup: its clock IDs start at CLK_INFRA_DBGCLK_PD (1), but the old code passed a gate offset of 0, so requesting e.g. CLK_INFRA_TRNG_PD resolved to the wrong gate. The offset is now taken from the first gate ID, like the other controllers. This also stops using mtk_common_clk_gate_init() and struct mtk_cg_priv, which are scheduled for removal. Signed-off-by: Julien Stephan <[email protected]> Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-7-23e907516010@baylibre.com Signed-off-by: David Lechner <[email protected]>
2026-07-29clk: mediatek: mt7623: use driver data to store the clock treeJulien Stephan
Pass each controller's struct mtk_clk_tree through the driver data and use the generic probe function for all the MT7623 clock drivers, instead of a dedicated probe per controller. The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since they rely on dedicated ops and on the parent bind() callback, but they now get their tree from the compatible data. The apmixedsys probe still performs its SoC specific register tweaks. No functional change intended. Signed-off-by: Julien Stephan <[email protected]> Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-6-23e907516010@baylibre.com Signed-off-by: David Lechner <[email protected]>
2026-07-29clk: mediatek: mt7623: deduplicate clock gate driversJulien Stephan
MT7623 declares a separate U_BOOT_DRIVER, probe() function and compatible table for each clock gate controller, despite all of them sharing the same implementation. Describe the gates directly in each controller's struct mtk_clk_tree, reference the trees from the driver data and use the generic mtk_clk_topckgen_ops. The ethsys and hifsys controllers, which share the same reset-binding bind() callback, are merged into a single U_BOOT_DRIVER; infracfg keeps its own driver since it is pre-relocation and does not bind a reset controller. This also stops using mtk_common_clk_gate_init() and struct mtk_cg_priv, which are scheduled for removal. No functional change intended. Signed-off-by: Julien Stephan <[email protected]> Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-5-23e907516010@baylibre.com Signed-off-by: David Lechner <[email protected]>
2026-07-29clk: mediatek: mt7622: use driver data to store the clock treeJulien Stephan
Pass each controller's struct mtk_clk_tree through the driver data and use the generic probe function for all the MT7622 clock drivers, instead of a dedicated probe per controller. The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since they rely on dedicated ops and on the parent bind() callback, but they now get their tree from the compatible data. The apmixedsys probe still performs its SoC specific register tweaks. The infracfg and pericfg controllers share the same ops, flags and (absent) bind() callback and are merged into a single driver. No functional change intended. Signed-off-by: Julien Stephan <[email protected]> Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-4-23e907516010@baylibre.com Signed-off-by: David Lechner <[email protected]>
2026-07-29clk: mediatek: mt7622: deduplicate clock gate driversJulien Stephan
MT7622 declares a separate U_BOOT_DRIVER, probe() function and compatible table for each clock gate controller, despite all of them sharing the same implementation. Describe the gates directly in each controller's struct mtk_clk_tree, reference the trees from the driver data and use the generic mtk_clk_topckgen_ops. Clock gate controllers that share the same DM flags and bind() callback can then share a single U_BOOT_DRIVER: the pciesys and ethsys controllers, which both bind a reset controller at the same offset, are merged into one driver, and the sgmiisys and ssusbsys controllers into another. This also stops using mtk_common_clk_gate_init() and struct mtk_cg_priv, which are scheduled for removal. No functional change intended. Signed-off-by: Julien Stephan <[email protected]> Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-3-23e907516010@baylibre.com Signed-off-by: David Lechner <[email protected]> (changed to CONFIG_IS_ENABLED)
2026-07-29clk: mediatek: mt8188: use driver data to store the clock treeJulien Stephan
Pass each controller's struct mtk_clk_tree through the driver data and use a single shared probe function for all the MT8188 clock drivers, instead of a dedicated probe per controller. The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since they rely on dedicated ops and on the parent bind() callback, but they now share the generic probe and get their tree from the compatible data, just like the clock gate controllers. No functional change intended. Signed-off-by: Julien Stephan <[email protected]> Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-2-23e907516010@baylibre.com Signed-off-by: David Lechner <[email protected]>
2026-07-29clk: mediatek: mt8188: deduplicate clock gate driversJulien Stephan
MT8188 currently declares a separate U_BOOT_DRIVER, probe() function and compatible table for each clock gate controller, despite all of them sharing the same implementation. Describe the gates directly in each controller's struct mtk_clk_tree, reference the trees from the driver data and use the generic mtk_clk_topckgen_ops. All the clock gate controllers can then share a single U_BOOT_DRIVER, eliminating the duplicated code. This also stops using mtk_common_clk_gate_init() and struct mtk_cg_priv, which are scheduled for removal. No functional change intended. Suggested-by: David Lechner <[email protected]> Signed-off-by: Julien Stephan <[email protected]> Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-1-23e907516010@baylibre.com Signed-off-by: David Lechner <[email protected]>
2026-07-29power: regulator: ADD PMIC PF9453 supportJoy Zou
Add regulator support for NXP PMIC pf9453 for imx91 qsb. Reviewed-by: Ye Li <[email protected]> Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Joy Zou <[email protected]> Signed-off-by: Peng Fan <[email protected]> Rebased [1] on main and LDO SNVS access / checkpatch fixed. See also [2] [1] https://patchwork.ozlabs.org/project/uboot/patch/[email protected]/ [2] https://lists.u-boot-project.org/pipermail/u-boot/2026-July/625613.html Signed-off-by: Krzysztof Drobiński <[email protected]>
2026-07-29power: pmic: ADD PMIC PF9453 supportJoy Zou
Support NXP PMIC pf9453. Reviewed-by: Ye Li <[email protected]> Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Joy Zou <[email protected]> Signed-off-by: Peng Fan <[email protected]> Rebased [1] on main and checkpatch fixed. See also [2] [1] https://patchwork.ozlabs.org/project/uboot/patch/[email protected]/ [2] https://lists.u-boot-project.org/pipermail/u-boot/2026-July/625613.html Signed-off-by: Krzysztof Drobiński <[email protected]>
2026-07-29power: domain: renesas-r8a78000: Add SDK SCP 4.36 mapMarek Vasut
The SCMI IDs did not change between SDK SCP 4.32 and SDK SCP 4.36. Add SDK SCP 4.36 as supported version and reuse SDK SCP 4.32 remap table. Signed-off-by: Marek Vasut <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2026-07-29mmc: enable CMD23 for multi-block transfersEric Chung
Enable the support for the CMD23 (SET_BLOCK_COUNT) command to manage multi-block read/write operations. This allows the MMC core to use CMD23 in preference to the legacy CMD18/CMD25 plus CMD12 sequence, reducing command overhead and improving I/O performance on multi-block transfers. Signed-off-by: Eric Chung <[email protected]> Signed-off-by: Tanmay Kathpalia <[email protected]> [ Drop MMC_CAP_CMD32 from mvebu_mmc.h ] Signed-off-by: Peng Fan <[email protected]>
2026-07-29mmc: fix mmc_deinit regression when card is at 1.8V signalingPeng Fan
Commit 906ee6785b1c ("mmc: sd: Handle UHS-I voltage signaling without power cycle") added detection of cards already operating at 1.8V signaling via mmc_sd_card_using_v18(). This correctly handles the warm-reboot scenario in mmc_startup(). However, mmc_deinit() strips ALL UHS capabilities from the card caps and calls sd_select_mode_and_width() to downgrade the card before kernel handoff. For a card that has switched to 1.8V, uhs_en is already true (via OCR_S18R in mmc->ocr), so sd_select_mode_and_width() attempts UHS mode selection -- but no UHS modes remain in the filtered caps. The non-UHS fallbacks (SD_HS, MMC_LEGACY) are 3.3V speed modes which, when selected while signaling at 1.8V, leave the card in an inconsistent state it cannot recover from without a power cycle. Per SD Physical Layer Specification: "Once the card enters 1.8V signaling mode, the card cannot be switched to 3.3V signaling without power cycle. If the card receives CMD0, card returns to Idle state but still works with SDR12 timing." Fix by using a UHS capability mask that preserves UHS_SDR12 when the card is operating at 1.8V. SDR12 is the minimum valid UHS-I mode and is always available at 1.8V signaling per the SD specification, so the card is left in a consistent (1.8V) state at a low, safe speed. Fixes: 906ee6785b1c ("mmc: sd: Handle UHS-I voltage signaling without power cycle") Reviewed-by: Tanmay Kathpalia <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2026-07-29mmc: fix mmc_bwrite() ignoring host get_b_max() callbackPeng Fan
mmc_bwrite() uses mmc->cfg->b_max directly to limit per-transfer block count. The read path (mmc_bread()) correctly calls mmc_get_b_max() which dispatches to the host driver get_b_max() callback. This callback allows host drivers to enforce DMA boundary constraints based on the buffer address. Fix mmc_bwrite() to use mmc_get_b_max() to match the read path. This requires removing the static qualifier from the non-DM mmc_get_b_max() and adding its declaration to mmc_private.h. Reviewed-by: Tanmay Kathpalia <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2026-07-29mmc: sdhci: fix align_buffer memory leak on re-initializationPeng Fan
sdhci_init() allocates a 512KB aligned bounce buffer for controllers with SDHCI_QUIRK_32BIT_DMA_ADDR. In the non-DM code path, sdhci_init() is registered as ops->init and called on every mmc_init(). Each call allocates a new buffer without checking or freeing the previous one, leaking 512KB per re-initialization. Fix by guarding the allocation with !host->align_buffer so it only allocates on the first call. Reviewed-by: Tanmay Kathpalia <[email protected]> Signed-off-by: Tanmay Kathpalia <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2026-07-29mmc: rpmb: fix tautological condition in RPMB_REQ_READ_DATA validationPeng Fan
In rpmb_route_frames(), the RPMB_REQ_READ_DATA case checks "req_cnt != 1 || !req_cnt" which is tautological -- !req_cnt (req_cnt == 0) is always a subset of req_cnt != 1. The second operand is dead code. Based on the pattern of all other cases in the switch (RPMB_REQ_KEY, RPMB_REQ_WRITE_DATA, RPMB_REQ_WCOUNTER) which validate rsp_cnt, this was meant to be "req_cnt != 1 || !rsp_cnt". Without this fix, a caller could pass rsp_cnt=0 for a read request without validation. Signed-off-by: Peng Fan <[email protected]>
2026-07-29mmc: fix mmc_poll_for_busy() false timeout when card is readyPeng Fan
mmc_poll_for_busy() returns a false -ETIMEDOUT if the card becomes ready on the exact iteration where timeout_ms reaches 0. The card-ready check breaks out of the loop, but then the post-loop check "if (timeout_ms <= 0)" fires and returns -ETIMEDOUT despite the card being ready. Fix by returning 0 directly when the card is ready instead of breaking out of the loop. The only exit from the loop is now the timeout path, so the post-loop code unconditionally returns -ETIMEDOUT. Reviewed-by: Tanmay Kathpalia <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2026-07-28ram: k3-ddrss: fix ecc range checking bugBin Liu
The original checking is wrong, it basically compares memory address end = r->start + r->range; with memory size: if (end > (ddr_ram_size - ecc_res)) so the if() condition would be always true. This causes the ECC config never take input from the devicetree. Fixes: f43f71012254 ("ram: k3-ddrss: Add support for a partial inline ECC region") Signed-off-by: Bin Liu <[email protected]> Reviewed-by: Neha Malcom Francis <[email protected]>
2026-07-28Kconfig: ram: select FDT_64BIT for K3_INLINE_ECCBin Liu
Commit f43f71012254 ("ram: k3-ddrss: Add support for a partial inline ECC region") uses ofnode_get_addr_size() to read memory address and size from devicetree using type fdt_addr_t and fdt_size_t. However these data types are 32bit if CONFIG_FDT_64BIT is not defined on ARMv7 build. So enable CONFIG_FDT_64BIT to retrieve correct 64bit memory address and size from devicetree. Signed-off-by: Bin Liu <[email protected]> Reviewed-by: Udit Kumar <[email protected]> Reviewed-by: Neha Malcom Francis <[email protected]>
2026-07-28cmd/mtd.c: fix do_mtd_io doesn't support 64bit user addressRomain Caritey
Signed-off-by: Romain Caritey <[email protected]>
2026-07-28board: phytec: phycore_am68x: Turn off pmic watchdogDominik Haller
Starting with pmic firmware version 5 the watchdog is enabled with a timeout window of 13 minutes by default. The TI EVMs use a dip switch to control a gpio on the pmic which gets configured as DISABLE_WDOG by the firmware. On the phycore_am68x there is no such dip switch so pull resistors would be necessary. Using mcu_i2c0 to turn off the pmic watchdog works with all hardware and pmic firmware combinations. Signed-off-by: Dominik Haller <[email protected]>
2026-07-28arm: dts: k3-am68-phyboard-izar-u-boot: Add mcu_i2c0Dominik Haller
Add mcu_i2c0 to access the pmic watchdog control registers. Signed-off-by: Dominik Haller <[email protected]>
2026-07-28serial: avoid redundant early UART initializationAswin Murugan
When DEBUG_UART and SKIP_EARLY_DM are enabled, the serial console is still probed before relocation even though DEBUG_UART already configures the UART and provides early console output. The debug UART configuration is sufficient until relocation, making full serial driver initialization at this stage unnecessary. Furthermore, the initialization is slow since it runs with dcache disabled and is repeated again after relocation. Skip pre-relocation serial probing in this configuration and defer full UART initialization until after relocation. Update the GENI UART probe logic accordingly. This removes redundant UART initialization and improves boot performance. Signed-off-by: Aswin Murugan <[email protected]>
2026-07-28arm: dts: Add SD dts for the sc598 EZKITCaleb Ethridge
The eMMC and SD card on the sc598 share pins, so they cannot be used at the same time. Previously, this was managed with a patch applied by the relevant build system, but patches are brittle and have to be maintained. Instead, they have been replaced with two separate device trees , one for eMMC and one for SD card, which inherit a shared base dtsi. The build system can then select between the default device tree which enabled eMMC or the other device tree which enables SD card support. Signed-off-by: Caleb Ethridge <[email protected]>
2026-07-28tools: binman: pass KEYDIR to FIT entriesJames Hilliard
U-Boot's Makefile passes KEYDIR to direct mkimage invocations, but internal binman FIT builds only receive the generic BINMAN_INDIRS search path. Adding KEYDIR to BINMAN_INDIRS treats it as one more input-file search path: FIT entries still auto-detect a key directory from all include directories, so an explicit KEYDIR may not be the directory that gets passed to mkimage. It also makes a key-only directory part of the generic blob lookup path. Forward KEYDIR as a binman entry argument named keydir, matching the existing entry-argument mechanism used for BL31, TEE, of-list and other U-Boot build inputs. FIT entries use that directory directly for mkimage -k when fit,sign or fit,encrypt is enabled, falling back to the include-directory autodetection when keydir is not provided. Signed-off-by: James Hilliard <[email protected]>
2026-07-28pinctrl: single: parse gpio-range as a raw array (O(N^2) -> O(N))Jordi Trepat Mur
single_add_gpio_func() calls ofnode_parse_phandle_with_args() once per gpio-range entry. With a flat device tree, every call re-iterates the property from index 0 and, because cellname is set, performs an fdt_node_offset_by_phandle() (a full-FDT scan) at every step. The total cost is therefore quadratic in the number of entries and proportional to the size of the device tree. The impact depends on when the pinctrl is probed. On the J722S EVM defconfig, pinctrl@f4000 (main_pmx0, the SoC's stock 7-entry gpio-range) is probed after relocation (caches on): single_add_gpio_func() takes ~18 ms there and ~1 ms with this change. When the node is probed before relocation (caches off) the same parse takes hundreds of ms; on a board that probes it pre-relocation and runs LPDDR4 clocked down it reached 723 ms, cut to 22 ms here. Any pinctrl-single user with a populated gpio-range property pays this cost. The phandle target is never dereferenced by this function (only the argument cells are stored), so resolve it only for the first entry to learn the per-entry cell count, then read the argument cells directly with ofnode_read_u32_index() and allocate the ranges in one block. A zero phandle still terminates the list, as in the original loop. This follows the existing pinctrl-single,gpio-range usage observed in current DTs, where entries use the same provider and therefore a uniform per-entry cell count. Signed-off-by: Jordi Trepat Mur <[email protected]> Reviewed-by: Anshul Dalal <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2026-07-28Merge patch series "Enable Ethernet boot on SK-AM62A-LP"Tom Rini
Chintan Vankar <[email protected]> says: This series enables Ethernet boot on SK-AM62A-LP. The series is based on commit 'a18265f1ccb7' of origin/next branch of U-Boot repo. Link: https://lore.kernel.org/r/[email protected]
2026-07-28doc: board: ti: am62ax_sk: Add document for Ethernet boot on AM62x SoC.Chintan Vankar
Document the procedure to enable Ethernet Boot on SK-AM62A-LP. Tested-by: Anshul Dalal <[email protected]> Signed-off-by: Chintan Vankar <[email protected]>
2026-07-28arm: dts: k3-am62a7-sk-u-boot: Enable DM services for main_pktdmaChintan Vankar
Enable DM services for main_pktdma during R5 SPL stage. Tested-by: Anshul Dalal <[email protected]> Signed-off-by: Chintan Vankar <[email protected]>
2026-07-28configs: am62ax_evm_a53_ethboot: Enable config options required to enable ↵Chintan Vankar
Ethernet boot Enable config options required to enable Ethernet boot on SK-AM62A-LP for A53 SPL stage. Acked-by: Andrew Davis <[email protected]> Reviewed-by: Anshul Dalal <[email protected]> Tested-by: Anshul Dalal <[email protected]> Signed-off-by: Chintan Vankar <[email protected]>
2026-07-28configs: am62ax_evm_r5_ethboot: Enable config options required for Ethernet bootChintan Vankar
The R5 SPL SRAM size is limited and cannot accommodate both MMC boot and Ethernet boot config options simultaneously. Add a dedicated defconfig that enables the Ethernet boot on SK-AM62A-LP for R5 SPL stage. Reviewed-by: Anshul Dalal <[email protected]> Tested-by: Anshul Dalal <[email protected]> Signed-off-by: Chintan Vankar <[email protected]>
2026-07-28Merge tag 'u-boot-nvme-next-20260728' of ↵Tom Rini
https://git.u-boot-project.org/u-boot/custodians/neil.armstrong/u-boot-nvme - nvme: Fix missing address translation for PCIe inbound access
2026-07-28Merge tag 'u-boot-ufs-fixes-20260728' of ↵Tom Rini
https://git.u-boot-project.org/u-boot/custodians/neil.armstrong/u-boot-ufs - ufs: invalidate the whole descriptor data segment after a query read
2026-07-28Merge tag 'efi-2026-01-rc2' of ↵Tom Rini
https://git.u-boot-project.org/u-boot/custodians/u-boot-efi Pull request efi-2026-01-rc2 CI: https://git.u-boot-project.org/u-boot/custodians/u-boot-efi/-/pipelines/753 Documentation: * sandbox: fix enum host_platform_flags description * switch from setenv to env set and from printenv to env print * document Renesas R-Car Gen5 RSIP Cortex-R52 start * thead: lpi4a: detail how to enable fastboot UEFI: * unify and correct GUID selection for security database variables * test: check default GUID selection of security database variables * set correct frame buffer address * check efi_deserialize_load_option() in get_dp_device()
2026-07-28Merge tag 'u-boot-dfu-20260728' of ↵Tom Rini
https://git.u-boot-project.org/u-boot/custodians/u-boot-dfu u-boot-dfu-20260728 CI: https://git.u-boot-project.org/u-boot/custodians/u-boot-dfu/-/pipelines/769 Android: * avb: Update libavb to AOSP 1.3.0 * avb: Fix memory leak on mmc_part * bootmeth_android: Fix memory leaks for AvbOps and verify-data * bootmeth_android: Fix out-of-bounds access in bootconfig parsing USB Gadget: * cmd: ums: Set serial# on iSerial device descriptor * dwc2: Set maxpacket_limit and endpoint capabilities to prepare for udc core migration * ci_udc: Fix ep type in ep_enable() * ci_udc: Set usb request status to handle complete callback * ci_udc: Ensure dtds are inactive before completing request
2026-07-27Merge tag 'u-boot-imx-main-20260727' of ↵Tom Rini
https://git.u-boot-project.org/u-boot/custodians/u-boot-imx CI: https://git.u-boot-project.org/u-boot/custodians/u-boot-imx/-/pipelines/749 - Support authenticating signed Mcore container image on i.MX9. - Support booting CM70, CM71 and CM33 sync cores on i.MX9. - Add i.MX SNVS RTC driver. - Detect RAM sizes on Toradex smarc and aquila i.MX95 boards. - Add support for the Librem5 devkit. - Subtract half a cycle instead of three quarters of a cycle after DQS gating calibration on i.MX6. - Several tqma6 improvements. - Add product ID support for new Toradex boards.
2026-07-27Prepare v2026.10-rc1v2026.10-rc1Tom Rini
Signed-off-by: Tom Rini <[email protected]>
2026-07-27Merge branch 'main' of ↵Tom Rini
https://git.u-boot-project.org/u-boot/custodians/u-boot-sunxi Beside a fix for a long standing bug in the A80 eMMC code, this adds SPI booting support for the Allwinner A523/A527/T527 class of boards. The second major feature is support for the secondary Ethernet controller on that same SoC. This might not be as important as for the kernel (I doubt that U-Boot acts as a router), but for once some boards only connect the secondary EMAC, and on others people might have the boot server only reachable via this port. There are some smaller fixes and improvements still queued up, but they need some more testing and are minor, so can land a bit later. The world build timed out, but the rest passed, and I booted that briefly on an A523 board with two Ethernet ports.
generated by cgit v1.3.1 (git 2.54.0) at 2026-09-04 03:16:49 +0000